RM57L843: Speculative fetches and cache

Marcio Borges

Expert 1950 points

Part Number: RM57L843

Hello,

I am trying to figure out whether I must do something about the errata "DEVICE#48 Interconnect Global Error flag is set after a CPU reset" or not.

We disabled the cache at the boot.

Do “speculative fetches” and “branch prediction” occur when the cache is disabled?

Thanks in advance.

over 2 years ago

+1 jagadish gundavarapu over 2 years ago

TI__Guru 69701 points

Hi Marcio,

The "speculative fetches" by CPU can be generate even if the "cache" is disabled. But this interconnect error flag is Group-1 ESM error right so it neither trigger ERROR signal nor abort, you can ignore it.

But if you still don't want that Group-1 error also then in that case you should follow the work around suggested in Errata.

Please refer below threads for further details:

(+) TMS570LC4357: TMS570lc43xx Errata ( Rev B): DEVICE#48 — Interconnect Global Error flag is set after a CPU reset. - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

(+) TMS570LC4357: Interconnect Self-Test Failure after LBIST / STC Success - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

Thanks & regards,
Jagadish.