Hello Support,
From the following link:
http://e2e.ti.com/support/microcontrollers/tms570/f/312/t/119516.aspx
I understand that I can initialize Parity Area of MibSPI RAM using nRESET as HIGH [toggling from ZERO] with SPIGCR0 Register.
Question is Parity is enabled through UERRCTRL Register's EDEN bit field.
Also UERRCTRL Register is accessible only when MIBSPIE Register's MSPIENA bit is set.
Also shown in the picture below about nRESET bit description.
Does this mean nRESET bit has to be 1 before CPU can access successfully UERRCTRL and MIBSPIE Registers?
I am assuming until and unless EDEN != 0x05, Parity Area will not be initialized with correct values.
So, I must make EDEN != 0x05 so that I can use Parity Error Detection successfully and auto-initialize Parity Area using nRESET Auto-Initialize feature.
Any detailed information will be helpful about how to use MibSPI Parity Error.
Thank you.
Regards
Pashan
