Hi Experts
When AM2732 is configured in RMII mode, we need to output RMII_MHZ_50_CLK to both CPSW and PHY.
we can use rmii_ref_clk_oe_n to select the where we can get the ref-clk. In both options, the clk loopback is inside our device, how to provide RMII_MHZ_50_CLK for external PHY?
Thanks
Ken
Hi Ken,
In AM273 ZCE package, the Ball number E19, Pad Name PADBX with Ball Name RCSS_GPIO_49, can be configured in Mux mode 2 to output the MSS_RMII_REFCLK. Please find more details about this in AM273 Datasheet Page 20 of 99.
The same can be configured through SYSCONFIG tool also as seen in below image.
Also please find hardware implementation details in TMDS273GPEVM, check for schematic in design files, Page 12 of 28, where the PHY has option to source clock from RCSS_GPIO_49(MSS_RMII_REFCLK on Mux Mode 2) through R341, a 0Ω resistor which is DNP/DNI by default.
Please let me know if this clarifies what you are looking for.
Thanks,
Tejas Kulakarni
