AM2632: Use of PRU-instance for extended IO-operation

Hello Jo Scho,

The PRU will have access to all GPIO of the AM263x to read or write (as does each R5F). However, it should be noted that PRU GPIO are not the same as the rest of the AM263x GPIO. The 20 GPIO from the PRU are Enhanced PRU GPIO which will have better performance in terms of latency and jitter. For additional information on the Enhanced PRU GPIO, refer to Chapter 7.2.5.2.2.3: Enhanced PRU GP Module and its subsections. 

Therefore, if your application is timing critical then it may not be ideal to make use of the other AM263x GPIO due to the increased jitter and latency. 

To configure the non-PRU GPIO:

• Find the address, respective bank, and bit of the GPIO
• Set the direction of the GPIO by writing to the respective MSS_GPIO_DIR<n> register's bit in the respective bank. 0 = output and 1 = input. By default all DIR is set to input.
• Configure outputs by writing to the MSS_GPIO_SET_DATA<n> register's bit in the respective bank. Output drive state of each GPIO is set to 0 by default. OUT_DATA<n> has no impact if the GPIO is configured as an input. 
• Read the output drive state by reading the MSS_GPIO_OUT_DATA<n> register
• Clear the output drive state by writing 1 to the respective bit in the MSS_GPIO_CLR_DATA<n> register
• For a GPIO configured as an input, read the input by reading the respective bit of the MSS_GPIO_IN_DATA<n> register.

<n> refers to the bank of the desired GPIO. Each bank is 16 bits and so a register will have two banks such as MSS_GPIO_DIR01 representing the direction mode of each gpio in banks 0 and 1. 

Regards,

Erik

Hi Erik,

thank you very much for your answer, but I have still some questions.

You say: The PRU will have access to all GPIO of AM263x.
Can the PRU access more than 20 GPIO at the same time, or is it limited to 20GPIOs, which are mapped to R30/R31?
Or is it limited to the 20GPIOs on the PRU?

How can I configure the GPIO-mapping of the PRI-GPIOs? Has this to be done on AM263x-side?

In general PRU-GPIO have a better performance in jitter/latency, is this correct?

Best regards

Jo Scho

Hello Jo Scho,

You can configure multiple GPIO in the same cycle with the R30/R31 registers for the PRU core based GPIO. Configuring R30 and R31 is independent of the GPIO Configuration for the AM263x GPIO bank which are configured using the process that I outlined in my previous response. If you want to configure GPIO for the PRU and the AM263x GPIO bank then it will not be able to be done in a single cycle of the PRU core. 

Jo Scho said:

How can I configure the GPIO-mapping of the PRI-GPIOs? Has this to be done on AM263x-side?

Can you provide additional detail to this question? To configure an output signal, the R30 register is to be used. Setting the respective bit in relation to the PR0_PRU0_GPIO<n> numeration in R30 will configure the GPIO as a logic-high output and clearing the respective bit will drive the output signal low.

Jo Scho said:

In general PRU-GPIO have a better performance in jitter/latency, is this correct?

That is correct, in relation to the performance of the AM263x GPIO. 

Regards,

Erik 

Hello Eric,

thanks for your answer.

Erik Friedel said:

Jo Scho said:

How can I configure the GPIO-mapping of the PRI-GPIOs? Has this to be done on AM263x-side?

Can you provide additional detail to this question? To configure an output signal, the R30 register is to be used. Setting the respective bit in relation to the PR0_PRU0_GPIO<n> numeration in R30 will configure the GPIO as a logic-high output and clearing the respective bit will drive the output signal low.

In detail we use at the moment the evaluation board AM263x_LP.
There we use the pin  B7 / GPIO26 as output (LED) and D14/GPIO123 as input (button), all done from R5F-Core0.
The question now is, can we do the IO-operation on these two pins also from PRU0-controller with R30/R311 (by usage of of XBAR?), or is IO-operation from PRU limited to the PRU-GPIO-pins? 

The second question:
Is the IO-operation from PRU limited to 20 GPIOs (in one cycle) or can we deal with more than 20GPIOs

Best regards
Jo Scho

Hello Jo, 

Jo Scho said:

The question now is, can we do the IO-operation on these two pins also from PRU0-controller with R30/R311 (by usage of of XBAR?), or is IO-operation from PRU limited to the PRU-GPIO-pins? 

The answer to your question is that you are able to configure the registers for each GPIO to toggle the output logic or read the input logic on the PRU core just as you would be able to on the R5 core. However, you will not be able to configure these GPIO through the use of the R30 and R31 registers of the PRU as these registers are specific to the 20 enhanced GPIO of the PRU core. 

Jo Scho said:

Is the IO-operation from PRU limited to 20 GPIOs (in one cycle) or can we deal with more than 20GPIOs

The input (R31) and output (R30) operation of the enhance GPIO of the PRU are able to be configured in one cycle. For the application above where GPIO26 is being toggled, this would have to be a separate operation from anything being done with R30 or R31 where the MSS_GPIO_SET_DATA<n> is set for the respective bit. 

Regards,

Erik

Hi Erik,

could you give me some code examples, for toogling GPIO26 from PRU0? Best regards, Jo Scho

Hello Jo Scho, 

I will work to provide you a code example. Please allow me until Thursday, end of day to provide the example. 

Regards,

Erik 

Hello Erik,

do you have some code example/project for us?

Regards
Jo Scho