Hi,
What is the clock to use to compute the "cycles" parameter of __delay_cycles()? PLL1 (300MHz), GCLK (300MHz), HCLK (150MHz)?
I am asking this question because the measurements I have done, do not match the GCLK clock (300MHz).
Best regards,
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Hi,
What is the clock to use to compute the "cycles" parameter of __delay_cycles()? PLL1 (300MHz), GCLK (300MHz), HCLK (150MHz)?
I am asking this question because the measurements I have done, do not match the GCLK clock (300MHz).
Best regards,
Hi Marchio,
What is the clock to use to compute the "cycles" parameter of __delay_cycles()? PLL1 (300MHz), GCLK (300MHz), HCLK (150MHz)?
It should be the CPU clock (GCLK). I never tested practically but as per my knowledge from old threads it should be CPU clock that is GCLK.
I am asking this question because the measurements I have done, do not match the GCLK clock (300MHz).
Can you please reverify your measurements?
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Thanks & regards,
Jagadish.
I did the measurements several times using a GPIO.
Maybe the error is because the cache is disabled and there is a delay to read the data from the internal flash. Also, the delay I want to count is too 100ms.
I´ll do more tests.
Thanks Jagadish.