TMDS570LS31HDK: Fully disable/block all interrupts, including FIQ

Hi Robin,

You can disable IRQ/FIQ exceptions within a Privileged mode by setting the CPSR.I bit and F bit to b1. _disable_interrupts() is to set I and F bits in CPSR, and  _enable_interrupts()  is to clear those two bits (I and F).

For more details refer below thread:

(+) TMS570LS1224: Disabling interrupts in IRQ handler causes return to invalid address - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

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Thanks & regards,
Jagadish.

Hi Jagadish,

Robin S said:

I have already used the CPSID AIF instruction to disable other interrupts, but I cannot control the FIQ interrupts,

I have already tried setting those bits within a privileged mode. I tried both the _disable_interrupts() function and the CPSID asm op directly.

There are multiple sources documenting the NMI behaviour of the FIQ:
https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/140945/fiq-disabling
https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1160270/tms570lc4357-using-arm-effectively/4363117?tisearch=e2e-sitesearch&keymatch=disable%2525252520fiq#4363117

https://www.ti.com/lit/an/spna218/spna218.pdf (Section 2.5)

I am looking for a workaround for this behaviour.

Thanks,

Robin

Hi Robin,

After doing research on old threads i found the following things:

FIQ is a non-maskable interrupt in Cortex-R4F, so it cannot be disabled. 

Out of reset, both IRQ and FIQ are disabled (I and F bits set in CPSR). Once FIQ are enabled (Clear F bit in CPSR) it is no more possible to disable it anymore.

Robin S said:

I am looking for a workaround for this behaviour.

So, there is no other way to disable FIQ except not to enable after RESET. So not enable FIQ interrupts to any other using interrupts and only use IRQ interrupts in your application.

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Thanks & regards,
Jagadish.

Hi Jagadish,

Thanks for helping me confirm this. Unfortunately there's no way to not enable FIQ interrupts as they're needed for things like the ESM handlers.

However, I did some testing and wanted to see if you could confirm the behaviour. I tried the following code to block interrupts, and as far as I could tell it could block a FIQ interrupt.

/* Disable interrupts. FIQ interrupts are unmaskable (spna218 Section 2.5)*/
 _disable_interrupt_();

 /* Change to FIQ mode to try and prevent FIQ interrupts. Best effort. */
 __asm(" MRS R0, CPSR");         /* Load the Current Program Status Register. */
 __asm(" BIC R0, R0, #0x1F");    /* Clear the Mode bits [4:0]. */
 __asm(" ORR R0, R0, #0x11");    /* Set the Mode to FIQ Mode (b10001). */
 __asm(" MSR CPSR, R0");         /* Save changes to CPSR. */

When viewing the CPSR, I can see the FIQ mode is set, but the F bit remains unset, meaning that interrupts should in theory happen:

I am concerned as when I browsed the ARM documentation (https://developer.arm.com/documentation/den0042/a/Exceptions-and-Interrupts/Exception-priorities/Exception-mode-summary)  it claims FIQ mode should mask this bit:

This is further supported by a natural FIQ manually remasking the bit:

It appears that my "workaround" does not do this properly, but I still saw the masking behaviour. Can you help me determine if I've done something that's just undefined behaviour or if this is what would be expected? Thank you.

Alternatively, is there a way to configure a software controlled FIQ?

Thanks for testing this Jagadish. I'll see if we can make a system level workaround for this then. Thanks!