AM2732-Q1: 90 VIM in lockstep

Hello123

Part Number: AM2732-Q1

5.37 Vectored Interrupt Manager (VIM)

In lockstep mode, core1 acts as a redundant copy of core 0. Interrupt routing will be through Core 0, but output from core 0 is compared with core 1 to provide sufficient diagnostic coverage. In

if VIM only contect to core 0, how does MCU do the compare between core0 and core1 ?

over 2 years ago

0 Shivasharan Nagalikar over 2 years ago

TI__Expert 8630 points

Started looking in to this, will update my initial comments by 08/01

Best regards, Shiv

+1 Shivasharan Nagalikar over 2 years ago in reply to Shivasharan Nagalikar

TI__Expert 8630 points

Hi,

I found this useful : https://community.arm.com/arm-community-blogs/b/embedded-blog/posts/comparing-lock-step-redundant-execution-versus-split-lock-technologies

For the query you raised please refer to: 6.1.5.7 VIM Lockstep Mode section in TRM. Extract here for quick reference:

In lockstep mode, CPU1 is used as a diagnostic for CPU0. In this mode, only the interrupt inputs for CPU0 are used. Besides to CPU0, these interrupt inputs are also internally routed to CPU1 (through the level-sync / edge-detect logic dedicated to CPU1, and additionally through some delay circuits). The outputs from both VIM interrupt cores are then sent to the MSS CCMR5 module through dedicated compare buses (with CPU0's outputs delayed). The CCMR5 module is responsible for comparing the two sets of output signals and for reporting any mismatches by generating an interrupt (MSS_CCMR5_ERR).

Please let me know if this answers your query ?

Best Regards, Shiv

0 Hello123 over 2 years ago in reply to Shivasharan Nagalikar

Intellectual 730 points

thank you very much. it can close.

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AM2732-Q1: 90 VIM in lockstep