MSPM0G3507: Programming flash of MSPM0G devices

Hi Edward

I recommend you can test the register and flash programming functionality using flashctl_multiple_size_write example on ..\mspm0_sdk_version\examples\nortos\LP_MSPM0G3507\driverlib\flashctl_multiple_size_write

Thanks!

Hi Xiaodong Li,

My code implementation was done according to example you specified, but flash remains blank.

Why programming operation fails, although the bits CMDPASS and CMDDONE of STATCMD register of NVM controller are ‘1’ at the end of the programming operation?

Thanks,

Hi Edward 

I checked this example code on launchpad and check if the memory has been programmed or not.

on memory browser on CCS. I can see the flash memory has been programmed.

CMDPASS and CMDDONE of STATCMD register have been set to 1 as well

Hi Xiaodong Li,

I have additional question about PWR-AP (Power access port) of the debug subsystem (DEBUGSS), which configures device power states.

According to SWD signals generated by Uniflash application, there are some operations with this AP before halting the core.

Where can I find document which describes registers of this access port?

Thanks

Hi Edward 

Please find the DEBUGSS register description on 26.5.2 DEBUGSS Registers of MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual

Thanks

Hi Xiaodong Li,

The paragraph 26.5.2 describes registers of SEC-AP port (Security access port), which executes operations with debug mailbox DSSM.

There are 5 access ports in the DEBUGSS (see table 26-1).

One of them is PWR-AP port, and I need description of registers of this access port.

Thanks

Hi Edward

Let me check this in detailed and reply to you later

Thanks

Hi Edward

I am out of office this week. I will check and feedback later.

Thanks

Hi Edward

Sorry to be late

Please check 26.5.2.13 SPECIAL_AUTH.PWRAPEN to enable and disable PWR-AP on MSPM0 G-Series 80-MHz Microcontrollers Technical Reference Manual

Thanks