• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 30 subscribers
  • Views 201 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2634-Q1: cache coherency problem for HSM service

Will Gao
Intellectual 2335 points
Part Number: AM2634-Q1

Hi BU, 

We use Secure IPC to get HSM service, and the data transfer is via pointer as below. For data transfer from R5F to M4, it is ok; but for data transfer from M4 to R5F, and if R5F using cache, there might be problem. I want to know the handle for cache coherency. Do you think in SDK we should add some operation to void the possible problem? 

Regards, 

Will 

  • +1
    TI__Mastermind 26145 points

    Hi Will,

    In order to inherit the HSM services, the application must comply the uses of IPC via shared memory i.e. a memory region should be designated to both the CPUs. However if the cache is enabled, for the shared region its application responsibility to bypass cache or invalidate the cache.

    The same is not captured in any documentation, so created an internal ticket for the same.

    Best Regards,
    Aakash