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TMS570LC4357: MibSpi slave

Ju_We
Intellectual 845 points

Part Number: TMS570LC4357

Hi All,

I am trying to use MibSPI3 in master mode and MibSPI5 in slave mode and exchange data between them.
Wiring:
SPI3.CS[0]  <------->   SPI5.CS[0]
SPI3.SIMO  <------->   SPI5.SIMO[0]
SPI3.SOMI  <------->   SPI5.SOMI[0]
SPI3.CLK    <------->   SPI5.CLK
I verified the correctness of the wiring and pinmuxing by using either interface in master and slave mode. The scope shows that the master generates CS, CLK and MOSI on either SPI.
However, the slave TG doesn't seem to be triggered. I am not sure if I undertand the concept correctly, this is what I do:

  uint16_t mTxDat[2] = {0x22EE, 0x4433};        // Charlen 8-Bit, Len = 1 => 0xEE
  uint16_t mRxDat[2] = {0};
  uint16_t sTxDat[2] = {0xBBF0, 0xDDCC};        // Charlen 8-Bit, Len = 1 => 0xF0
  uint16_t sRxDat[2] = {0};
  
  mibspiInit();
  
  mibspiSetData(mibspiREG3, 0, &mTxDat[0]);     // setup tx-data for master
  mibspiSetData(mibspiREG5, 0, &sTxDat[0]);     // setup tx-data for slave
  
  mibspiTransfer(mibspiREG5, 0);                // trigger TG0 slave
  mibspiTransfer(mibspiREG3, 0);                // trigger TG0 master
  
  while(mibspiIsTransferComplete(mibspiREG3, 0) == FALSE);      // works        
  while(mibspiIsTransferComplete(mibspiREG5, 0) == FALSE);      // infinite wait

  mibspiGetData(mibspiREG3, 0, &mRxDat[0]);
  mibspiGetData(mibspiREG5, 0, &sRxDat[0]);

Halcogen-Settings:
Does anyone know what I am missing?

Thanks,
Juergen

  • 0
    TI__Guru* 77556 points

    Hi Juergen,

    Recently i created one master and slave examples for MibSPI using ENA pin, here are these projects:

    5556.MibSPI_Master_with_ENA_TEST_LC4357.zip

    8468.MibSPI_Slave_with_ENA_TEST_LC4357.zip

    As above projects uses ENA pin i am also attaching one master project with CS0 pin.

    MibSPI1_TEST_LC4357 (2).zip

    So please do refer all of these three projects and do the necessary modifications on your side and do the testing. If the issue still not resolved after referring them then i will do the debugging of your projects at my end.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 845 points

    Hi Jagadish, 

    your project looks basically the same. The only difference is, that I am using one CPU, you seem to use two. Does that matter at a point?
    I've kept playig a little. I set the slave (SPI 5) to classic SPI mode, just to narrow down things. For the master (SPI 1) I tried classic and MibSpi mode. If both, the master and the slave, are in in classic mode, everything works as excpected. Setting the master to MibSpi mode troubles me. The slave still receives something, but the data is incorrect. The data format is set identically to the one in classic SPI mode and for now I am unly tranferring 2 Bytes by setting Charlen to 16. I wouldn't expect to see a differnce between classic SPI and MibSpi mode.

    Regards,
    Juergen

  • 0 in reply to Ju_We
    TI__Guru* 77556 points

    Hi Juergen,

    Ju_We said:
    The only difference is, that I am using one CPU, you seem to use two. Does that matter at a point?

    No, It should not.

    Can you please attach your code by configuring both Master and Slave in MibSPI. I will do the debug and will provide an update.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 845 points

    Hi Jagadish, 

    I was working with a custom board. Hence, I prepared a HDK project for you to be able to debug my problem. But as I was doing that, I have learnt two things:
    - I needed to increase to CS to TX start delay
    - MibSpi5 never sent the response when its used as a slave. I had trouble finding out why that is. I connected a scope to CS, CLK, SIMO and SOMI and noticed that SOMI kept floating. As if it doesn't care for its CS being low. My transfer group uses CS[0]. It doesn't seem to be allowed to set CS[1], CS[2],  CS[3] and CS[0] also to functional (SPI). As soon as I set their function to GIO, MisSPI5 actively sent the response on SOMI. I don't really know what this is the case, but at lease it works. Maybe you can point where in the datasheet I can find that information.

    Best Regards,

    Juergen

  • 0 in reply to Ju_We
    TI__Guru* 77556 points

    Hi Juergen,

    Can you please send the code, so i can debug and see the issue.

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 845 points

    Hi Jagadish,

    here's the project with the same problem. MibSPI3 ist master, MibSpi5 is the slave, they both work on CS[0]. If I set any of the other CS in MibSpi5 to functional. while(mibspiIsTransferComplete(mibspiREG5, 0) == FALSE);  does not return.

    Regards,
    Juergen

    5722.DMASPI.zip

  • 0 in reply to Ju_We
    TI__Guru* 77556 points

    Hi Ju We,

    I found the problems with your code.

    There are couple of problems i observed.

    1. You should not configure multiple chip-selects in slave side

    You should only configure one chip select i.e. either CS0 or CS1, if you enable both the chip selects then the slave will expect active chip selects on both CS0 and CS1 to shift the data. So just select one chip select and use the same chip select at Transfer Group configurations.

    2. You configured TG0 buffer Lenth as 1, so due this you can be able to receive only one 16bit data only. 

    Configure TG0 buffer length as 2 in both master and slave sides.

    If you test now, then you can see the proper transmission of data between the master and slave.

    Here is your project after i did the modifications, take this as reference and do the necessary modifications on your side.

    0184.DMASPI.zip

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Intellectual 845 points

    Hi Jagadish,

    I am aware of all of these 'issues'. Buffer length as 1 was merley for test purposes. I did figure out that setting more than one CS to SPI mode causes the slave to keep its SOMI line in HI-Z state. It's only the case for SPI5, not for SPI3. That's why I asked you previously where in the reference manual I can find that information. It's just very surprising that SPI3 and SPI5 behave differently in that regard. 

    Regards,
    Juergen