TMS570LC4357: How to use SPI RX Interrupt

Hi Jagadish, 

thanks for your help, it worked. Now I am trying SPI and with DMA. SPI3 is the master, SPI5 the slave. On the scope I can see that the DMA must trigger transfers because SPI3 outputs a clock signal and CS goes low. But SIMO line stays low, I can't figure out why. Here's my code:

#define SPI_MASTER_TX_SIZE              5

uint32_t mTxDat[SPI_MASTER_TX_SIZE] = {
  0x103EA1A2,    // FMT = 0, CS=CS0, HOLD=1, Data = 0xA1A2
  0x103EA3A4,    // FMT = 0, CS=CS0, HOLD=1, Data = 0xA3A4
  0x103EA5A6,    // FMT = 0, CS=CS0, HOLD=1, Data = 0xA5A6
  0x103EA7A8,    // FMT = 0, CS=CS0, HOLD=1, Data = 0xA7A8
  0x003EA9AA,    // FMT = 0, CS=CS0, HOLD=0, Data = 0xA9AA
};

uint16_t sRxDat[SPI_MASTER_TX_SIZE];

g_dmaCTRL g_dmaCTRLPKT_SPI3_TX;
g_dmaCTRL g_dmaCTRLPKT_SPI5_RX;

#define DMA_SPI3_RX_CH          DMA_CH14
#define DMA_SPI3_TX_CH          DMA_CH15
#define DMA_SPI3_RX_REQ         DMA_REQ14
#define DMA_SPI3_TX_REQ         DMA_REQ15

#define DMA_SPI5_RX_CH          DMA_CH30
#define DMA_SPI5_TX_CH          DMA_CH31
#define DMA_SPI5_RX_REQ         DMA_REQ30
#define DMA_SPI5_TX_REQ         DMA_REQ31

int main(void)
{
    spiInit();

    spiREG3->INT0 &= ~0x0300U;                                                    /* DMA => turn off RX/TX ints  */
    spiREG5->INT0 &= ~0x0300U;

    g_dmaCTRLPKT_SPI3_TX.SADD      = (uint32)(&mTxDat);                           /* source address               */
    g_dmaCTRLPKT_SPI3_TX.DADD      = (uint32)(&spiREG3->DAT1);                    /* destination  address         */
    g_dmaCTRLPKT_SPI3_TX.CHCTRL    = 0;                                           /* channel control              */
    g_dmaCTRLPKT_SPI3_TX.FRCNT     = SPI_MASTER_TX_SIZE;                          /* frame count                  */
    g_dmaCTRLPKT_SPI3_TX.ELCNT     = 1;                                           /* element count                */
    g_dmaCTRLPKT_SPI3_TX.ELDOFFSET = 0;                                           /* element destination offset   */
    g_dmaCTRLPKT_SPI3_TX.ELSOFFSET = 0;                                           /* element source offset        */
    g_dmaCTRLPKT_SPI3_TX.FRDOFFSET = 0;                                           /* frame destination offset     */
    g_dmaCTRLPKT_SPI3_TX.FRSOFFSET = 0;                                           /* frame source offset          */
    g_dmaCTRLPKT_SPI3_TX.PORTASGN  = PORTA_READ_PORTB_WRITE;                      /* rd from RAM, wr to periph    */
    g_dmaCTRLPKT_SPI3_TX.RDSIZE    = ACCESS_32_BIT;                               /* read size                    */
    g_dmaCTRLPKT_SPI3_TX.WRSIZE    = ACCESS_32_BIT;                               /* write size                   */
    g_dmaCTRLPKT_SPI3_TX.TTYPE     = FRAME_TRANSFER;                              /* transfer type                */
    g_dmaCTRLPKT_SPI3_TX.ADDMODERD = ADDR_INC1;                                   /* address mode read            */
    g_dmaCTRLPKT_SPI3_TX.ADDMODEWR = ADDR_FIXED;                                  /* address mode write           */
    g_dmaCTRLPKT_SPI3_TX.AUTOINIT  = AUTOINIT_OFF;                                /* autoinit                     */

    g_dmaCTRLPKT_SPI5_RX.SADD      = (uint32_t)((uint32)&(spiREG5->BUF) + 2);     /* source address               */
    g_dmaCTRLPKT_SPI5_RX.DADD      = (uint32)(&sRxDat);                           /* destination  address         */
    g_dmaCTRLPKT_SPI5_RX.CHCTRL    = 0;                                           /* channel control              */
    g_dmaCTRLPKT_SPI5_RX.FRCNT     = SPI_MASTER_TX_SIZE;                          /* frame count                  */
    g_dmaCTRLPKT_SPI5_RX.ELCNT     = 1;                                           /* element count                */
    g_dmaCTRLPKT_SPI5_RX.ELDOFFSET = 0;                                           /* element destination offset   */
    g_dmaCTRLPKT_SPI5_RX.ELSOFFSET = 0;                                           /* element source offset        */
    g_dmaCTRLPKT_SPI5_RX.FRDOFFSET = 0;                                           /* frame destination offset     */
    g_dmaCTRLPKT_SPI5_RX.FRSOFFSET = 0;                                           /* frame destination offset     */
    g_dmaCTRLPKT_SPI5_RX.PORTASGN  = PORTB_READ_PORTA_WRITE;                      /* red from periph, wr to RAM   */
    g_dmaCTRLPKT_SPI5_RX.RDSIZE    = ACCESS_16_BIT;                               /* read size                    */
    g_dmaCTRLPKT_SPI5_RX.WRSIZE    = ACCESS_16_BIT;                               /* write size                   */
    g_dmaCTRLPKT_SPI5_RX.TTYPE     = FRAME_TRANSFER ;                             /* transfer type                */
    g_dmaCTRLPKT_SPI5_RX.ADDMODERD = ADDR_FIXED;                                  /* address mode read            */
    g_dmaCTRLPKT_SPI5_RX.ADDMODEWR = ADDR_INC1;                                   /* address mode write           */
    g_dmaCTRLPKT_SPI5_RX.AUTOINIT  = AUTOINIT_OFF;                                /* autoinit                     */

    dmaSetCtrlPacket(DMA_SPI3_TX_CH, g_dmaCTRLPKT_SPI3_TX);
    dmaReqAssign(DMA_SPI3_TX_CH, DMA_SPI3_TX_REQ );
    dmaSetChEnable(DMA_SPI3_TX_CH, DMA_HW);

    dmaSetCtrlPacket(DMA_SPI5_RX_CH, g_dmaCTRLPKT_SPI5_RX);
    dmaReqAssign(DMA_SPI5_RX_CH, DMA_SPI5_RX_REQ);
    dmaSetChEnable(DMA_SPI5_RX_CH, DMA_HW);

    spiREG5->INT0 |= 0x00010000;    /*  DMA REQ EN                                      */

    dmaEnable();

                     /* DMA REQ EN => kicks off 1st DMA transfer when SPI is enabled   */
    spiREG3->INT0 = (spiREG3->INT0 & 0x0000FFFFU) | 0x00010000;
    
}

Here's the CCS project:

6765.DMASPI.zip

Hi Jagadish,

your example drives the MOSI line. I don't know why mine doesn't, ok.

Regards,
Juergen