MSPM0G1507: Inconsistent datasheet in pinout for 24 VQFN package

In the MSPM0G150x datasheet (revised June 2023), there are many inconsistencies in the datasheet's pinouts for the VQFN package:

• Page 14: UART0_TX is listed in pins PA0 (pin 24), and PA10 (pin 9), whereas on page 27 only the pin 11 is indicated for UART0_TX
• SPI0_POCI in the same way is indicated on PA4 (pin 7), PA10 (pin 9) in the per-pin table and on pin 11 in the per-peripheral table.

Many more examples of this exist, at which point we don't know what to trust in the datasheet.

The same inconsistencies do not appear for the 64-pin package (which seem to match correctly between the two tables).

Especially, the pinouts of the following peripherals are needed for our application:

• UART0
• SPI0
• I2C0
• JTAG signals (SWDIO/SWCLK)
• VDD/VSS and NRST
• 5 or so more pins used for GPIO (we have to check they are not reserved for something else e.g. NRST, JTAG...)

This is the case despite the MSPM0G1507 being available only in the 24 VQFN package on ti.com website.