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TM4C1290NCZAD: SPI communication mechanism question

xi.yan.kiana
Intellectual 430 points
Part Number: TM4C1290NCZAD
Other Parts Discussed in Thread: MSP430FR5994

Hi,teams:

     Now,I want to use TM4C1290NCZAD  and  MSP430FR5994  to  transfer some data with SPI communication. 

  In my system, TM4C is the master and MSP430 is the slave. 

 The host sends a request frame, and then the host continues to send some virtual signals to generate a clock signal,

after the slave receives the command from the host, since the clock signal on the bus is normal at this time, the slave

Able to send data back to the host normally. 

We all know that SPI is full-duplex communication.But in the process I described, SPI seems to be a half-duplex communication.

When the host sends data, the slave needs to rely on the clock signal generated by the host to send some virtual signals (such as 0XFF)

to send its own data back to the host.

If during this process, due to some reasons, there is a problem with the clock signal, then the SPI will fail to send and receive data.

So i really want to know
（1）SPI full-duplex communication, how does the master and slave send and receive data at the same time,

why does the master not need to provide an additional clock signal to the slave?

（2）At present, the problem we have encountered is that occasionally the SPI communication between

the two chips cannot be communicated. Is it feasible for the master to send a virtual signal to generate a clock signal for the slave?

Please forgive my long-winded.I hope that some experts can patiently help me answer it after seeing it.

  • 0
    TI__Guru**** 191886 points

    Hi,

    xi.yan.kiana said:
     The host sends a request frame, and then the host continues to send some virtual signals to generate a clock signal,

    Can you please clarify what is your virtual signals to generate clock?

    Are you not using the on-chip SPI module to generate the SPI clocks? If you are not using SPI module then what is the reason not using it?

    Are you suggesting you are using a bit-bang method to generate the SPI clocks using GPIO module?

    xi.yan.kiana said:

    If during this process, due to some reasons, there is a problem with the clock signal, then the SPI will fail to send and receive data.

    So i really want to know
    （1）SPI full-duplex communication, how does the master and slave send and receive data at the same time,

    SPI is a full-duplex operation, meaning that in the presence of SPI clocks, data is being sent on the TX pin by the master while the slave sends its data on the RX pin. If there is a problem with the clock then it can cause both sides to mis-interpret the completion of the data transmission. For example, if there is some noise on the clock signal, it may lead the slave to mis-interpret as an extra clock or maybe missing clock edges. 

    xi.yan.kiana said:
    why does the master not need to provide an additional clock signal to the slave?

    I don't understand your question here. If you use the hardware SPI module which I recommend instead of using a software method to bit-bang the protocol then the number of clock pulses is controlled by the hardware. There is no additional clock to generate by the master unless you are talking about some noises on the bus. If that is the case, it is a system level issue on your schematic that you need to take care of. 

    xi.yan.kiana said:

    （2）At present, the problem we have encountered is that occasionally the SPI communication between

    the two chips cannot be communicated. Is it feasible for the master to send a virtual signal to generate a clock signal for the slave?

    Please elaborate what is not working. Again what is virtual signal signal? Is it using software method to generate SPI clock? I do not recommend this method for real time operation. 

  • 0 in reply to Charles Tsai
    Intellectual 430 points

    Thank you very much for your very detailed reply, maybe my expression is not very clear, some places have misunderstood you, Let me answer your question first.

     xi.yan.kiana said:

    The host sends a request frame, and then the host continues to send some virtual signals to generate a clock signal,

    Can you please clarify what is your virtual signals to generate clock?

    ------ The dummy signal refers to 0xFF.

    Are you not using the on-chip SPI module to generate the SPI clocks? If you are not using SPI module then what is the reason not using it?

    ------I use the on-chip SPI module to generate the clock signal.

    Are you suggesting you are using a bit-bang method to generate the SPI clocks using GPIO module?

    ------I have not used this method

    xi.yan.kiana said:

    （2）At present, the problem we have encountered is that occasionally the SPI communication between

    the two chips cannot be communicated. Is it feasible for the master to send a virtual signal to generate a clock signal for the slave?

    Please elaborate what is not working. Again what is virtual signal signal? Is it using software method to generate SPI clock? I do not recommend this method for real time operation. 
    ------- It may be that the clock signal is generated by software
    I grabbed the request frame data sent by the master and slave, and tried to describe the whole process to you completely.
    Case 1：

    The host sends a request frame： (note:   channel0:  SPI CLOCK     channel1: CS(unused)   channel2: Master device    channel3: slave device)

    0xAA  0xBB  0x06  0x02  0x00  0x00  0x00  0x00  0x00  0x00  0x00  0x00  0xCC  0xDD

    After sending the request frame, the host continues to send 0xFF to  generate the SCLK signal(0XFF is what I call a virtual signal)  

    Slave replies data to master

    Case 2 ：After I tried the host to send a request frame, the host does not continue to send 0XFF，and the waveform is as follows:

    The host sends a request frame：

    Since there is no clock signal, the data sent by the slave will not appear on the bus

    Finally, I would like to ask, the current SPI communication mechanism seems to generate clock signals through software. If there are indeed problems with this method, I would like to ask, is there any other way to generate SPI clock signals? Can you describe in detail how to generate the clock signal? If there are related routines, you can refer to it.

  • 0 in reply to xi.yan.kiana
    TI__Guru**** 191886 points

    Hi Kiana,

      Thank you for your waveform captures. Can you tell me what triggers your code to send 0xFF on the master side? Is it based on what is received from the slave?

      If you look at case 1, while you are sending 0xAA  0xBB  0x06  0x02  0x00  0x00  0x00  0x00  0x00  0x00  0x00  0x00  0xCC  0xDD, you are receiving 0x44, 0x44.....0x44 from the slave? Is this what you are expecting to receive?

      If you look at case 2, while you are sending 0xAA  0xBB  0x06  0x02  0x00  0x00  0x00  0x00  0x00  0x00  0x00  0x00  0xCC  0xDD, you are receiving 0x88, 0x88....0x88 which is different from case 1. Is possible that on the master side, if it receives non-0x44 then it will not send out the virtual clocks with 0xFF? It looks like there is a one-bit shift between 0x44 and 0x88. You will need to investigate this. Please make sure both sides have identical baudrate. Check if there is any noise on the bus as the noise may cause the slave to misinterpret as a valid clock. When this happens, it sends the data too early resulting in a shift. You will need to use a oscilloscope to see this.  I will suggest you focus on the first character you send. In case 1, when you send 0xAA on the master request frame, you are receiving 0x44 (01000100b). In case 2, you are receiving 0x88 (10001000b). Find out why there is a one bit shift.