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TMS570LC4357-EP: TMS570LC4347-EP

Part Number: TMS570LC4357-EP

Hello Support Team,

We are planning to use TMS570LC4347-EP in our projects because of its lockstep feature. However DO-178C standards limit us, so that we would like to ask you some questions;

1- How does the lockstep feature work in TMS570LC4347-EP?

2- Is it possible to use split mode with TMS570LC4347-EP?

3- Can the second core work independently?

4- If 3rd question is not, how does the second core use memory?  Same or different?

5- If both cores uses same memory, how are the input registers of both core designed?

6- In the technical reference, there was a figure (in page 499 figure 13-1.Block Diagram) and it seems there are two independent input registers for both core but this is a discrete case of lockstep phenomenon, can you explain this figure as well?

Thank you in advance for your answers,

Halil 

  • Hi Halil,

    1- How does the lockstep feature work in TMS570LC4347-EP?

    The lockstep is the mode of operation of the dual ARM Cortex-R5F CPUs. The device has one module called CCM-R5F. During CPU lockstep mode, the outputs of the two CPUs are compared on each CPU clock cycle by this module. Any miscompare is flagged as an error of the highest severity level. The outputs of the two VIMs in lockstep are also compared on each cycle by this module.

    The two processors are initialized to the same state during system start-up, and they receive the same inputs, so during normal operation the state of the two processors is identical from clock to clock.

    An error in either processor will cause a difference between the states of the two processors, which will eventually be manifested as a difference in the outputs. The CCM-R4F module monitors the outputs of the two processors and flags an error in the case of a discrepancy.

    2- Is it possible to use split mode with TMS570LC4347-EP?

    No, not possible to work in split mode. The CPU's are always works in lockstep mode.

    3- Can the second core work independently?

    No, it won't work independently because the second core is just a checker CPU which is just helpful to check the main CPU. 

    4- If 3rd question is not, how does the second core use memory?  Same or different?

    Same as Main CPU, the only difference is the inputs are delayed by a two clock cycles for checker CPU and for main CPU the outputs are delayed by two clock cycles, and CCM module will compare the both the outputs and generates error if any miscompare happens.

    5- If both cores uses same memory, how are the input registers of both core designed?

    Both cores will have separate register set. And CCM module will also compares the values of these register set and generates error if they are differed.

    6- In the technical reference, there was a figure (in page 499 figure 13-1.Block Diagram) and it seems there are two independent input registers for both core but this is a discrete case of lockstep phenomenon, can you explain this figure as well?

    Not all internal registers of the Cortex-R4F CPU have fixed values upon reset. To avoid an erroneous CCMR4F compare error, the application software needs to ensure that the CPU registers of both CPUs are initialized with the same values before the registers are used, including function calls where the register values are pushed onto the stack.

    Please refer below threads for more details:
    (+) TMS570LS3137: Dual CPUs Running in Lockstep - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums
    (+) TMS570LS3137: Lockstep verification and intended behavior of the CPUs - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

    --

    Thanks & Regards,
    Jagadish.

  • Hey Mr Jagadish,

    It will be very helpfull. Thank you very much.

    Have a nice day,

    Halil