TM4C1290NCPDT: BSDL issue

Hi,

  Your device TM4C1290NCPDT has a 128-pin QFP package while TM4C1290NCZAD is uses a 212-pin BGA package. This is the reason they have different DR length. because the number of I/O pins on the packages are different.  

Dear,

probaly i wasn't  so clear,

I have on the pcb this device:TM4C1290NCPDT a 128-pin QFP

but i get from data register 411 bit instead 258 bit as described into BSDL, why?

Could it be related to upgrade of production using same silicon of bga version and the device model wasn't updated?

Hi,

  What type of tool do you use to determine the boundary scan length for TM4C1290NCPDT is 411? As far as I can see, I see the BSDL file say the boundary scan length is 285. See below. 

For the TM4C1290NCZAD it is 411 as defined in the BSDL file. 

Hi Charles,

I'm using XJTAG, during checkCahin test it check ID code, IR lengt and DR length,

it seems that the 128 QFP device has the same DR of BGA device,

if I use the BSDL of QFP device I get error on length of DataRegister, test enviroment expect 285 bit as descibed into bsdl but found 411 bit,

I tried to use BSDL of BGA device after i modified the section PIN_MAP:STRING, i removed the one included into BGA bsdl and copy there the one of QPF bsdl,

then the test works fine i also was able to check some pin togling it, but before i use my "BSDL" i'd like to get some clarification from TI, the best would be to get an

updated BSDL for QFP device from TI.

Best Regards

Hi,

"These BSDL files have been out there for years. We would have seen the same reporting as this is a very apparent discrepancy"

So I think it was posted some years ago, the question is: is the component TM4C1290NCPDT now the same of the one when the BSDL was generated?

Could be possible that TI developed a new component used into BGA package (where there are more pins/ports) and than use the same silicon inside QFP package linking only the used ports on present pins?

To measure the length of any register we select that register and then scan a marker value into TDI and count the number of clocks that are required for this data to come out of TDO.

In the case of the BSR we use the SAMPLE instruction to select the register so that the data that is left in the register does not affect what the device does at the end of the checking process.

So I almost sure your BSDL are wrong at least it does' t applyable to current version of component.

Please could you check it.

Thanks

Hi,

 Honestly, I'm confused myself on this subject.  As you know there is only one silicon die but there are multiple packages being supported from the 212p BGA package to the 128p QFP package. This means that some I/Os are bonded out to the BGA package but not on the QFP package. From the boundary scan chain point of view, this was already hardwired in the silicon. Therefore, no matter what package is used, the length of the scan chain should be fixed. Unless my understanding is wrong, we can't really change how the different scan cells are connected in the chain depending on what package the silicon is pinned out. From this perspective the 411 you read out seems to make sense for any package. However, my understanding about BSDL file is that it carries the information about what pins you can do for boundary scan test (e.g. INTEST, EXTEST). If an internal I/O pad is not bonded out in a QFP package, then what good is it do any EXTEST and INTEST on this I/O pad. This is why I also think the BSDL file for QFP package is also correct. I'm not knowledgeable on the boundary scan test and I don't know if your boundary scan test tool XJTAG has any options to mask out I/O pads that are not bounded out. 

Hi Charles,

the first step was done, if you confirm that there is only one silicon die.

Then there are some section in BSDL,

the first

entity 

port (

list of port.. 

...

the second

PIN_MAP_STRING:=

list of which port is connected to pin number

PD0   1

PD1 2

The third  that is interesting 

attribute BOUNDARY_REGISTER

where is described the register i call DATA REGISTER

" 0 (BC_1, *, CONTROL, 1 ), " &
" 1 (BC_1, PD7, OUTPUT3, X , 0, 1, Z ), " &
" 2 (BC_1, PD7, INPUT, X ), " &
" 3 (BC_.....

this is related to silicon die not to the package so it is composed by 411 bit also if it is fitted into qfp package, do you agree?

Inside the model available on TI website for component tm4c1290ncpdt it is composed by 285 bit it's the error.

I'm olso not expert on BSDL, I hope i was able to explain enough to get back the fixed BSDL.

Best Regards

Giuseppe Russo said:

" 0 (BC_1, *, CONTROL, 1 ), " &
" 1 (BC_1, PD7, OUTPUT3, X , 0, 1, Z ), " &
" 2 (BC_1, PD7, INPUT, X ), " &
" 3 (BC_.....

this is related to silicon die not to the package so it is composed by 411 bit also if it is fitted into qfp package, do you agree?

 The BSDL file for this section specifies 'boundary' cells. The key word is boundary cells, not any cells. If you further look into this section, there is no PB6 and PB7 because these two pins are not bonded out in the QFP package but in BGA package. 

  Take for example the line you pasted as follows, this boundary cell is an output cell associated with the logical pin name PD7. 

" 1 (BC_1, PD7, OUTPUT3, X , 0, 1, Z ), " &

If you look under the PIN_MAP_STRING section starting at line 160, the logic pin PD7 is associated with the physical pin 128 in a QFP package. Let's go back to the PB6 or PB7. These two pins are not bonded out and therefore, they do not show up neither in the BOUNDARY_REGISTERS section nor in the PIN_MAP_STRING section. If your XJTAG or whatever JTAG scan tool finds a scan cell for PB6 or PB7 then they should be masked out but I don't know what it takes to mask them as I don't know these tools. 

Please also refer to this webpage https://www.xjtag.com/about-jtag/bsdl-files/bsdl-and-svf-file-formats/ for BSDL details. It has the below description in the article. If you read the BSDL file on how the power, ground and analog pins are defined, they are defined as 'linkage'. This means the file was originally generated prior to 2013. It has been 10 years since and honestly, you are the first one to report the file does not work. This is why I wonder why no one encountered the same issue in the last couple of years after I started to support this product. 

Any connections that cannot be used for boundary scan such as power or analogue pins are defined as “LINKAGE” (in BSDL files created before the 2013 standard). Devices compliant with the 2013 or later versions of the standard differentiate between such pins: for example, a power pin may be defined as “POWER_NEG” and an analogue pin could be “LINKAGE_OUT”.

I finished my resource, 

the boundary cells are in the silicon die not on the pin copper if the boundary cell are persent in the silicon die it has be described into boundary scan register.

Sorry but are you TI employer? 

Or What else?

sorry 

it had to be described into boundary scan register...

Hi Gluseppe,

I'm a TI employee. As much as I'd like to help, these BSDL files were supposed to be generated by the design team when the design was completed. I think they are the derivatives of the silicon design by running some EDA tool to extract the boundary scan chain information.  Unfortunately, the design for this product was done many years (maybe 10+ years) ago and I have a hard time to find someone who knows more about generating a BSDL file for this device let alone the design database is not available, most likely on archive already. I'm not a designer, unfortunately. You mentioned that you sort of hack the BSDL file for BGA by copying the PIN_MAP section from the QFP device over and it is working. By doing so, I believe all the boundary cells that are not mentioned in the QFP BSDL will be automatically NC (no connect). If this is the case, I think that is the best alternative to resolve your issue. I'm still surprised that for so many years, no one reported the same issue. I tried to search the forum archive for similar reporting to no avail. I will bookmark this post incase someone reports the same issue in the future. 

Hi Charles,

I apologize for last email,

I hope you understand my disappointment,

It seems we have determinated the model is not correct, the solution is I have to modify the model myself.

Even if I can do that, or to say it better I've already done, I think it's not the right way to go ahead, my customer that is also TI customer buy from TI thousands of component, TI has the design authority on the BSDL of component that TI sell so TI has to release a working version of BSDL.

Pleae, let me know if you're yoing to do it or not.

If I wont receive answer I have to share with your customer this issue.

Best Regards

Giuseppe

Hi Giuseppe,

  As I mentioned we already don't have a design team supporting this device. I will need to reach out to different team to understand several things. 

 - How was the BSDL generated?

 - Is it correct for the existing BSDL? Namely, the boundary scan chain length is different for different packages.

  -Is the design database still available?

  -If there is a flaw in the BSDL file, can BSDL be regenerated.

I promise I will write back if I have some update. Please understand this is going to take some time to resolve. Please also understand I'm an application engineer support the forum for this product and I don't have the history as to how these BSDL files were generated by the design team. 

Hi Giuseppe,

  Here is some update. As in my last reply, I'm still trying to understand the process on how and why the existing BSDL files were generated the way they are today. In the meantime, please find the attached BSDL file that is hand-edited. Please give it a try. 

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/tm4c1290ncpdt_5F00_ra0_5F00_tqfp_5F00_v0p1_5F00_new.bsdl