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Hi Team,
There's an issue from the customer need your help:
、
Configure according to Table 23-9, disable the input buffer of pin pin[n]. When N2HET is running, using the PCNT command can still capture the actual running level width on pin[n] .
Thanks & Regards,
Ben
Hi Jagadish,
Disable the input buffer by configuring DIR=0, PULDIS=1, and PULSEL=0 corresponding to pin 1, as shown in 1 and 3 in the figure. Observe that the value of the DIN register is changing, and the value captured by pin 1 is 0 or 1. As shown in Figure 2 above, the current value captured by pin 1 is 1.
Best Regards,
Ben
//het指令程序源码
B0 CNT { next=B1,reg=A,max=4,data=0};
B1 ECMP { next=B2,hr_lr=LOW,en_pin_action=ON,cond_addr=B2,pin=10,action=PULSEHI,reg=A,data=1,hr_data=0x00};
B2 PCNT { hr_lr=LOW,next=B0,type=RISE2FALL,pin=1,control=ON,prv=OFF,data=0};
*****************************************************************************
//C语言代码
//het指令对应的结构体
static const hetINSTRUCTION_t HET_INIT0_PST[3] =
{
/* B0_0 */
{
0x00002C20,
0x00000004,
0x00000000,
0x00000000
},
/* B1_0 */
{
0x00004100,
0x00404A18,
0x00000080,
0x00000000
},
/* B2_0 */
{
0x00000E61,
0x04000000,
0x00000000,
0x00000000
}
};
static const hetINSTRUCTION_t HET_INIT2_PST[2] =
{
/* B0_0 */
{
0x00002C20,
0x00000001,
0x00000000,
0x00000000
},
/* B1_0 */
{
0x00000100,
0x00400018,
0x000000DA,
0x00000000
}
};
//het初始化函数
/** @fn void hetInit(void)
* @brief Initializes the het Driver
*
* This function initializes the het 1 module.
*/
/* SourceId : HET_SourceId_001 */
/* DesignId : HET_DesignId_001 */
/* Requirements : HL_CONQ_HET_SR10 */
void hetInit(void)
{
int i = 0x10000;
/** @b initialize @b HET */
/** - Set HET pins default output value */
hetREG1->DOUT = (uint32)((uint32)0U << 31U)
| (uint32)((uint32)0U << 30U)
| (uint32)((uint32)0U << 29U)
| (uint32)((uint32)0U << 28U)
| (uint32)((uint32)0U << 27U)
| (uint32)((uint32)0U << 26U)
| (uint32)((uint32)0U << 25U)
| (uint32)((uint32)0U << 24U)
| (uint32)((uint32)0U << 23U)
| (uint32)((uint32)0U << 22U)
| (uint32)((uint32)0U << 21U)
| (uint32)((uint32)0U << 20U)
| (uint32)((uint32)0U << 19U)
| (uint32)((uint32)0U << 18U)
| (uint32)((uint32)0U << 17U)
| (uint32)((uint32)0U << 16U)
| (uint32)((uint32)0U << 15U)
| (uint32)((uint32)0U << 14U)
| (uint32)((uint32)0U << 13U)
| (uint32)((uint32)0U << 12U)
| (uint32)((uint32)0U << 11U)
| (uint32)((uint32)0U << 10U)
| (uint32)((uint32)0U << 9U)
| (uint32)((uint32)0U << 8U)
| (uint32)((uint32)0U << 7U)
| (uint32)((uint32)0U << 6U)
| (uint32)((uint32)0U << 5U)
| (uint32)((uint32)0U << 4U)
| (uint32)((uint32)0U << 3U)
| (uint32)((uint32)0U << 2U)
| (uint32)((uint32)0U << 1U)
| (uint32)((uint32)0U << 0U);
/** - Set HET pins direction */
hetREG1->DIR = (uint32) 0x00000000U
| (uint32) 0x00000000U
// | (uint32) 0x00000004U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000c00U
// | (uint32) 0x00000400U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U;
/** - Set HET pins open drain enable */
hetREG1->PDR = (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U;
/** - Set HET pins pullup/down enable */
hetREG1->PULDIS = (uint32) 0x00000000U
| (uint32) 0x00000002U
// | (uint32) 0x02000000U
// | (uint32) 0x00040000U
// | (uint32) 0x00800000U
// | (uint32) 0x00080000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U;
/** - Set HET pins pullup/down select */
hetREG1->PSL = (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U;
/** - Set HET pins high resolution share */
hetREG1->HRSH = 0;
#if 0
(uint32) 0x00008000U
| (uint32) 0x00004000U
| (uint32) 0x00002000U
| (uint32) 0x00001000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000008U
| (uint32) 0x00000004U
// | (uint32) 0x00000002U
| (uint32) 0x00000001U;
#endif
/** - Set HET pins AND share */
hetREG1->AND = (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
// | (uint32) 0x00000020U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
// | (uint32) 0x00000002U
| (uint32) 0x00000000U;
/** - Set HET pins XOR share */
hetREG1->XOR = (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
// | (uint32) 0x00000020U
// | (uint32) 0x00000022U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U;
/* USER CODE BEGIN (1) */
#if 0
//loopback,pin10-11
hetREG1->LBPSEL = (0x20U<<0U) //LBPSEL,1-enable loopback
| (0x20U<<16U); //LBPTYPE,0-digital,1-analog
hetREG1->LBPDIR = (0xA<<16) //LBP Test enable key
| (0x20<<0U); //0:1->0,1:0->1
#endif
#if 0
//loopback,pin0-1
hetREG1->LBPSEL = (0x1U<<0U) //LBPSEL,1-enable loopback
| (0x1U<<16U); //LBPTYPE,0-digital,1-analog
hetREG1->LBPDIR = (0xA<<16) //LBP Test enable key
| (0x0<<0U); //0:1->0,1:0->1
#endif
// het_loopback_enable(hetREG1,10,1);
/* USER CODE END */
/** - Setup prescaler values
* - Loop resolution prescaler
* - High resolution prescaler
*/
hetREG1->PFR = (uint32)((uint32) 3U << 8U)
| ((uint32)0U);
/** - Parity control register
* - Enable/Disable Parity check
*/
//hetREG1->PCR = (uint32) 0x00000005U;
hetREG1->PCR = (uint32) 0x0000010AU;
/** - Fill HET RAM with opcodes and Data */
/*SAFETYMCUSW 94 S MR:11.1,11.2,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
/*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
/*SAFETYMCUSW 95 S MR:11.1,11.4 <APPROVED> "HET RAM Fill from the table - Allowed as per MISRA rule 11.2" */
// (void)memcpy((void *)hetRAM1, (const void *)het1PROGRAM, sizeof(het1PROGRAM));
//SSYU
(void)memcpy((void *)hetRAM1, (const void *)HET_INIT0_PST, sizeof(HET_INIT0_PST));
/** - Setup interrupt priority level
* - PWM 0 end of duty level
* - PWM 0 end of period level
* - PWM 1 end of duty level
* - PWM 1 end of period level
* - PWM 2 end of duty level
* - PWM 2 end of period level
* - PWM 3 end of duty level
* - PWM 3 end of period level
* - PWM 4 end of duty level
* - PWM 4 end of period level
* - PWM 5 end of duty level
* - PWM 5 end of period level
* - PWM 6 end of duty level
* - PWM 6 end of period level
* - PWM 7 end of duty level
* - PWM 7 end of period level
* - CCU Edge Detection 0 level
* - CCU Edge Detection 1 level
* - CCU Edge Detection 2 level
* - CCU Edge Detection 3 level
* - CCU Edge Detection 4 level
* - CCU Edge Detection 5 level
* - CCU Edge Detection 6 level
* - CCU Edge Detection 7 level
*/
hetREG1->PRY = (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U;
/** - Enable interrupts
* - PWM 0 end of duty
* - PWM 0 end of period
* - PWM 1 end of duty
* - PWM 1 end of period
* - PWM 2 end of duty
* - PWM 2 end of period
* - PWM 3 end of duty
* - PWM 3 end of period
* - PWM 4 end of duty
* - PWM 4 end of period
* - PWM 5 end of duty
* - PWM 5 end of period
* - PWM 6 end of duty
* - PWM 6 end of period
* - PWM 7 end of duty
* - PWM 7 end of period
* - CCU Edge Detection 0
* - CCU Edge Detection 1
* - CCU Edge Detection 2
* - CCU Edge Detection 3
* - CCU Edge Detection 4
* - CCU Edge Detection 5
* - CCU Edge Detection 6
* - CCU Edge Detection 7
*/
hetREG1->INTENAC = 0xFFFFFFFFU;
hetREG1->INTENAS = (uint32) 0x00000001U
| (uint32) 0x00000002U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000010U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000080U
| (uint32) 0x00000100U
| (uint32) 0x00000000U
| (uint32) 0x00000400U
| (uint32) 0x00000800U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U
| (uint32) 0x00000000U;
hetREG1->EXC1 = 1<<8;//Program Overflow Enable
/** - Setup control register
* - Enable output buffers
* - Ignore software breakpoints
* - Master or Slave Clock Mode
* - Enable HET
*/
hetREG1->GCR = ( 0x00000001U
| (uint32)((uint32)0U << 24U)
| (uint32)((uint32)1U << 16U) //1master or 0slave
| (0x00000000U));//0x00020000U
}
Hi Ben,
Apologies in the delay response.
I am on vacation for one week. Today i will try to reproduce your issue and will try to provide an update ASAP.
--
Thanks & regards,
Jagadish.
Hi Ben,
Can you please refer below thread once?
It looks same issue we are facing now:
(12) Input Buffer Disable on NHET - HalCoGen Default Is Disable - Different Behavior with Emulator Attached/Unattached - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums
Here they are saying without emulator the input buffer disabling for the above configuration we mentioned and with emulator the input buffer is not disabling.
So, how do you test at your end?
Is it without debugger or with debugger?
If with debugger, then can you please test without debugging?
--
Thanks & regards,
Jagadish.