MCU-PLUS-SDK-AM243X: Built-in Self-test

Jonas Reich said:

it is a Build-in Self-test when a Core test the other Cores and not itself?

The CPU selftest controller (STC) is used to test the Cortex-R5 core using the deterministic logic built-in selftest (LBIST) controller as the test engine. There are two STCs for two Cortex-R5 cores. Performing LBIST on Core 1 doesn't affect core2.

Jonas Reich said:

How the PBIST procedure work exactly?

The PBIST architecture consists of a small coprocessor with a dedicated instruction set targeted specifically toward testing memories. This coprocessor executes test routines stored in the PBIST ROM and runs them on multiple on-chip memory instances. The on-chip memory configuration information is also stored in the PBIST ROM.

The MCU core can select the algorithm and RAM groups for the memories' self-test from the on-chip ROM based on the application requirements. Once the self-test has executed, the CPU can query the PBIST controller registers to identify any memories that failed the self-test.

Before starting the test, the MCU needs to program the ALGO register (PBIST_C12) to decide which algorithm from the instruction ROM must be selected, and program the RINFOL (PBIST_C13) and RINFOU (PBIST_RAMT) registers to indicate whether a particular RAM group in the instruction ROM would get executed or not. The memory bitmapping and Algorithm bitmapping are not listed on current TRM and datasheet. I am trying to find this information for you. 

March13 is the most recommended algorithm for the memory self-test.

Jonas Reich said:

There is no explanation (in API, code) which fixed defines (PBIST2) are for which instance

As far as I know, the PBIST2 is Cortex-R5 core 0 PBIST instance, and PBIST3 is the Cortex-R5F core 1 instance. 

Jonas Reich said:

What is important to consider, when i want to use the BIST?

The PBIST tests are destructive to memory contents. The contents of the selected memory before the test will be completely lost. You can retain SRAM content by copying the data from the SRAM to be tested to a non-tested memory before test execution and to restore the data once the test is complete. After test execution is complete, I suggest to run the hardware-based SRAM initialization which programs the memory to a known state with correct ECC.

Jonas Reich said:

Can I change the fixed defines (like SDL_PBIST2_ALGO_BITMAP_0) ?

Yes, you can try different algorithm for the selected RAM. Be aware of that If an algorithm is selected to run on an incompatible memory, this will result in a failure. For example March31N is selected to test a ROM.

Hello QJ Wang,

Thank you for your fast response.

Where can I get all this information, is there any documentation for this?

When there isn't yet, perhaps it make sense to document this information in the SDK or the Technical Reference Manual.

It is good to know, which memory bitmappings and Algorithm bitmappings are supported.

For me it is not clear yet, which Memory is tested exactly and how I can change this.

Hi Jonas,

Jonas Reich said:

Where can I get all this information, is there any documentation for this?

I recognize how critical this is. I will keep you informed upon I get it.

Hello is there any new information of this Topic ?

Hi Jonas,

I haven't got the info. I will check it out today.

HI Jonas,

I will list the RAM IDs and test Algorithms this weekend for you. Apologizes for delayed response.

Hello!

Where can I find a detailed description about the BISTs of the AM243x, especially the BISTs that can be executed over the R5F CPUs and their memories? How to invoke, sideeffects, which parameters, chunk sizes, ...? I tried the TRM of the AM243x. There are references to some BIST registers but there is no special description.

Who can help me out?