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TM4C123GH6PM: SPI communications and handling of FSS on the Tiva-C

Part Number: TM4C123GH6PM

Hello,

I initialize my spi peripheral on the tm4c123 as:

    // SSI0 initialization
    SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

    GPIOPinConfigure(GPIO_PA2_SSI0CLK);
    GPIOPinConfigure(GPIO_PA3_SSI0FSS);
    GPIOPinConfigure(GPIO_PA4_SSI0RX);
    GPIOPinConfigure(GPIO_PA5_SSI0TX);
    GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5 | GPIO_PIN_4 | GPIO_PIN_3 | GPIO_PIN_2);
    SSIConfigSetExpClk(SSI0_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 4000000, 8);
    SSIEnable(SSI0_BASE);

And I was expecting FSS to be handled automatically. But however I failed getting read results from my spi sensor, untilI removed the GPIOPinConfigure(GPIO_PA3_SSI0FSS); statement and configured PA4 to be GPO port, handling the CS of the SPI myself.

Here are read and write register functions:

void writeReg(uint8_t addr, uint8_t data) {

    uint32_t dummy[1];

    addr = addr & 0x7F;

    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0x00);

    SSIDataPut(SSI0_BASE, addr);
    SSIDataPut(SSI0_BASE, data);
    while(SSIBusy(SSI0_BASE));

    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);

    while (SSIDataGetNonBlocking(SSI0_BASE, &dummy[0]));

}

uint8_t readReg(uint8_t addr) {

    uint32_t dummy[1];
    uint32_t data;

    addr = addr | 0x80;

    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0x00);

    SSIDataPut(SSI0_BASE, addr);
    SSIDataGet(SSI0_BASE, &dummy[0]);
    SSIDataPut(SSI0_BASE, 0x00);
    SSIDataGet(SSI0_BASE, &data);

    while(SSIBusy(SSI0_BASE));
    GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3);

    while (SSIDataGetNonBlocking(SSI0_BASE, &dummy[0]));

    return (uint8_t)(data & 0xFF);


}

Although they work now, under what circumstances we dont have to manage  CS of the SPI peripherals ourselves? Does the FSS drop low with each SPI get put statement? Notice that to read from a register, I willput the addr byte first, then get a byte and then pull up the CS line.

Best Regards,

C.A.

  • Hi Can,

    untilI removed the GPIOPinConfigure(GPIO_PA3_SSI0FSS); statement and configured PA4 to be GPO port, handling the CS of the SPI myself.

    Yes, handing the CS using the GPIO port is the most robust way. This is what I will recommend to customers. The Fss pin on TM4C123 will de-assert (raising it high) at every word transfer. Please refer to the datasheet for details. Below is an excerpt. Having said that, on TM4C129 MCU there exists the feature to hold the Fss active low during continuous transfers until it is stopped by the application. But that is not the case for TM4C123. 

    However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed
    High between each data word transfer because the slave select pin freezes the data in its serial
    peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
    device must raise the SSInFss pin of the slave device between each data transfer to enable the
    serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned
    to its idle state one SSInClk period after the last bit has been captured.