• State
  • Locked Locked
  • Replies 11 replies
  • Subscribers 35 subscribers
  • Views 530 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2732: Access to RCSS SCI A UART example code

Atique Rehman
Prodigy 10 points
Part Number: AM2732

Hi,

I am trying to access RCSS_SCI_A (UART) port using the UART port example provided as part of drivers. 

We are trying to make sure that all 4 UART port are accessible from either core of MCU. So far I have modified the UART example to access MSS_SCIA, MSS_SCIB, DSS_SCIA, they all word perfectly fine when programmed using said example. In the next phase I want make sure that RCSS_SCI_A is also accessible using the UART example. I modified the UART example to configure the RCSS_SCI_A port. When tested there is no error in configuration part of the code and it works as per expectation. Next when I try transmit a byte on RCSS_SC_A Tx channel, it always stuch in TxReady flag check. This flag always return false. Also tried to pull low RTS pin but result os still same.

My questions are:

  • Is RCSS_SCI_A accessible from MSS code (or simply UART driver example code)?
  • Is there any example code available to verify the functionality of RCSS_SCI_A UART?
  • If it can be accessed from UART example code, what changes I need to do to make it work?

I am using dev kit TMDS273GPEVM.

Thanks,

Atique 

  • 0
    TI__Prodigy 100 points

    Hi,

    Apologies for delay. Please share the IO mux details.. As the application you made is working on the other instances, I don't suspect from programming part of it except the IOMUX. 

    Can you elaborate on the board connection w.r.t to PAD_DC & PAD_DD and also read the values of the below mentioned IO Mux registers and share it across.

    1) PAD_DC : Address - 0x020C0140  [RCSS_SCIA_RX]

    2) PAD_DD : Address - 0x020C0144  [RCSS_SCIA_TX]

    Regards

    Rakesh

  • 0 in reply to Rakesh Y C
    Prodigy 10 points

    Hi,

    I am using TMDS273GPEVM rev C board for testing.

    IO Mux Details are: 

        /* RCSS_UARTA_RX -> PAD_DT (B16) */
    {
        PIN_PAD_DT,
        ( PIN_MODE(2) | PIN_PULL_DISABLE )
    },
    /* RCSS_UARTA_TX -> PAD_DS (A17) */
    {
        PIN_PAD_DS,
        ( PIN_MODE(2) | PIN_PULL_DISABLE )
    },
    /* RCSS_UARTA_CTS -> PAD_DQ (A18) */
    {
        PIN_PAD_DQ,
        ( PIN_MODE(2) | PIN_PULL_DISABLE )
    },

     Board Connections:

    As per this documents EVM User Guide page 25 following changes are made to the board RCSS_UARTA is not available in the standard hardware configuration of the AM273x EVM. However, this port can be accessed if resistors R160 and R164 are depopulated with resistors R156 and R159
    populated with 0 ohm resistors. This alteration will make RCSS_UARTA_RX and RCSS_UARTA_TX accessible via the FTDI USB port (J8) as replacements of the DSS_UART interface.

    As far as PADs are concerned RCSS TX and RX is located on PAD_DS (TX) A17 and PAD_DT (RX) B16 as per the Datasheet of Micro page 26 and 27. Also schematic part of the EVM is as per this picture:

    This detail is available under the design resources of EVM in zip file.

    So the relative PAD s will be:


    1) PAD_DS : Address - 0x020C0180   [RCSS_SCIA_TX]   value-> 0x00000102

    2) PAD_DT : Address - 0x020C0184   [RCSS_SCIA_RX]   value-> 0x00000102

    Thanks

    Atique

  • 0
    TI__Prodigy 460 points

    Hi,

    RCSS_SCI_A is accessible from DSS code,  because both DSS and RCSS are accessible through the FTDI USB port (J10) via the FT4232HL UART - USB Bridge whereas MSS is accessible through XDS USB port.

    And there is no specific  example code for the RCSS_SCI_A. We can do by modifying the code as PADD DD ---> PIN MUX MODE (6) for RCSS_UART_TX and PADD DC---> PIN MUX MODE (5) for RCSS_UART_RX.  Not only with this combination there are many PADs that have modes allotted for RCSS, we can use any of them. Like you said with PAD_DS and PAD_DT also RCSS can be accessible.

  • 0 in reply to Narayanarao Puli
    Prodigy 10 points

    Hi,

    I have modify the board by depopulating the resistors R160 and R164, while populating R156 and R159 with 0 ohm resistors. So on my board RCSS UART connection to the FTDI port are using PAD_DS and PAD_DT. It would have been simpler I have modified he PAD_DD and PAD_DC functions only.

  • 0 in reply to Atique Rehman
    TI__Prodigy 460 points

    Hi,

    Is it now working or still facing the issues?

  • 0 in reply to Narayanarao Puli
    Prodigy 10 points

    Hi

    Still not working, facing the same issue

  • 0 in reply to Atique Rehman
    TI__Prodigy 460 points

    Hii,

    Sorry for the delay. I am working on it, will update by 15/09/23

  • 0 in reply to Narayanarao Puli
    TI__Prodigy 460 points

    Hi,

    These are the steps needs to be followed and It worked on my setup and able to transmit and receive 1 byte of data.

        • Enable IOs, Find the correct IO pads  PAD_DS-->mux mode(2) and PAD_DT-->mux mode(2) and  enable them by writing 0x102 value to addresses 0x020C0180 and 0x020C184 respectively.
        • Enable UART (SCI_GCR0->1), enable asynch mode with RX and TX and internal SCLK enable (SCI_GCR1-> 0x3000022)
        • Keep some initial data in SCI_TD register
        • Configure SCI clock select to 200MHz clock ( write x222 in RCSS_SCIA_CLK_SRC_SEL (address- 0x0500001C) and 0x0 in RCSS_SCIA_CLK_DIV_VAL address-0x05000058)
        • Configure SCI Baud Rate. There are 2 BR registers, Integer( RCSS_SCI_A_UARTIBRD (address- 0x050C0024)) and fraction(RCSS_SCI_A_UARTFBRD (address- 0x050C0024)) . I fixed it for 115200
        • I= Hex(Clock frequency/(16*BR))
        • F=Hex(64*(Decimal part of Clock frequency/(16*BR))
        • Enable UART, TX and RX (RCSS_SCI_A_UARTCR((address- 0x050C0030->1), enable FIFO, and set number of characters to 7 (8bits) (RCSS_SCI_A_UARTLCR_H (address- 0x050C002C)->x70)
        • Set FIFO Watermark level (RCSS_SCI_A_UARTIFLS(address- 0x050C0034)->0x8)
        • Enable All Interrupts (RCSS_SCI_A_UARTIMSC(address-0x050C0038)->0x7FF)
        • Enable DMA TX/RX (RCSS_SCI_A_UARTDMACR(address-0x050C0048)->0x2)
        • Configure Baud rate(SCI_SCIBAUD), char length of data(SCI_SCICHAR) (BAUD, CHAR)
        • Configure IOs to TX and RX (IO 1, 8) SCI_SCIPIO0, SCI_SCIPIO8

      You can use Tera term to view the received data.

    • 0 in reply to Narayanarao Puli
      Prodigy 10 points

      Hi, 

      Are you sure that you are using the AM273x or dev kit TMDS273GPEVM. Because I am not able to find the most of the register listed above in TRM of AM273x.

      Register list that I have for UART is: (from TRM page 2524)

      offset   Name  
00h      SCIGCR0
04h      SCIGCR1
0Ch      SCISETIN
10h      SCICLEARINT
14h      SCISETINTLVL
18h      SCICLEARINTLVL
1Ch      SCIFLR
20h      SCIINTVECT0
24h      SCIINTVECT1
28h      SCIFORMA
2Ch      BRS     
30h      SCIED   
34h      SCIRD   
38h      SCITD   
3Ch      SCIPIO0 
40h      SCIPIO1 
44h      SCIPIO2 
48h      SCIPIO3 
4Ch      SCIPIO4 
50h      SCIPIO5 
54h      SCIPIO6 
58h      SCIPIO7 
5Ch      SCIPIO8 
90h      IODFTCTRL

      One thing I have noticed while debugging that SCIGCR0 always 0 (UART is in reset state) and SCIGCR1 is also 0.

      Thanks,

      Atique

    • 0 in reply to Atique Rehman
      TI__Expert 7525 points

      Hi Atique,

      Sorry for the delay. Yes We are using the AM273x EVM but may be different version (But that should not be a problem . We will check  and come back by 25th on the registers answer as expert on this is out currently. Apologies for incovinience.

      Best Regards, Shiv 

    • 0
      TI__Prodigy 460 points

      Hii,

      These are the registers you can use for the transmission and reception of data through RCSS.

      RCSS_SCI_A           0x050C0000 (base address)

                      Register                                  Offset

      RCSS_SCI_A_UARTDR                        0x00
      RCSS_SCI_A_UARTRSR_ECR            0x04
      RCSS_SCI_A_UARTFR                        0x18
      RCSS_SCI_A_UARTILPR                    0x20
      RCSS_SCI_A_UARTIBRD                   0x24
      RCSS_SCI_A_UARTFBRD                  0x28
      RCSS_SCI_A_UARTLCR_H                0x2C
      RCSS_SCI_A_UARTCR                       0x30
      RCSS_SCI_A_UARTIFLS                    0x34
      RCSS_SCI_A_UARTIMSC                   0x38
      RCSS_SCI_A_UARTRIS                      0x3C
      RCSS_SCI_A_UARTMIS                     0x40
      RCSS_SCI_A_UARTICR                     0x44
      RCSS_SCI_A_UARTDMACR              0x48

      We will update the TRM with these registers. Apologies for the inconvenience.

      Best regards,
      Narayanarao Puli