RM57L843: LPOCLKDET and PLL Slip detector and ESM interrupt

Hi Marcio,

Marcio Borges said:

Besides reading the Global Status Register (GLBSTAT), do they trigger an ESM interrupt? 

Yes, they can trigger the ESM interrupt.

If you refer the datasheet, then you can find them in ESM group-1 channels.

And the Group-1 ESM channels have a configurable interrupt generation

So, you just need to enable the corresponding bit in the interrupt enable register.

So, you have to set the following bits.

So, you can just call the above function with corresponding channel number to enable the interrupt generation.

once you did that then, whenever the corresponding interrupt occurs then the ESM module will notify the interrupt using the function "esmGroup1Notification"

So, you can add your required definition in the esmGroup1Notification function.

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Thanks & regards,
Jagdish.

Thank you.

Section "14.5.3 Behavior on PLL Fail" of SPNU562A–March 2018 says:
When BPOS[1:0] is enabled (BPOS[1:0] = 00b OR 01b OR 11b):
• PLL slip causes the clock source into GCM clock source 1 to shift from the PLL to the oscillator
• ESM/exception is generated
• reset on slip is generated if ROS is set

I beleve the interrupt and the reset cannot be use at the same time.

Maybe the better strategy to announce the error would be wait the cpu to recover from the reset, use System Exception Status Register (SYSESR) to determine the cause of the reset and then signal the error. What do you think?

Best regards