RM46L852: N2HET IRQ and VIM Parity error

Hi Nuno,

In which function the code getting stuck?

Is it stuck at the "vimParityCheck" function?

If possible, can you please provide your code to debug the issue at our end, you can send private message if you need.

--

Thanks & Regards,
Jagadish.

The code is getting stuck in VimParityErrorHandler()

/** @file sys_main.c 
*   @brief Application main file
*   @date 11-Dec-2018
*   @version 04.07.01
*
*   This file contains an empty main function,
*   which can be used for the application.
*/

/* 
* Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com 
* 
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*/


/* USER CODE BEGIN (0) */
/* USER CODE END */

/* Include Files */

#include "sys_common.h"

/* USER CODE BEGIN (1) */
#include "rti.h"
#include "het.h"
#include "gio.h"
#include "PWM.h"
#include "sys_dma.h"
/* USER CODE END */

/** @fn void main(void)
*   @brief Application main function
*   @note This function is empty by default.
*
*   This function is called after startup.
*   The user can use this function to implement the application.
*/

/* USER CODE BEGIN (2) */
void dmaConfigCtrlPacket(uint32 sadd,uint32 dadd,uint32 dsize);
void delay();
uint8 TX_DATA[]={0xaa,0x55};
uint8 RX_DATA[]={0x0,0x0};
void hetNotification(hetBASE_t *het, uint32 offset);
g_dmaCTRL g_dmaCTRLPKT;
void createTxDummyPacket(uint8_t *packet, uint32_t size);

unsigned int phetREG1DOUT8;
/* USER CODE END */

int main(void)
{
/* USER CODE BEGIN (3) */

    phetREG1DOUT8 =  0xFFF7B854 + 0x3;
//    phetREG1DOUT8= &(hetREG2->DOUT) + 3;


    _enable_IRQ();

    dmaReqAssign(DMA_CH0,24);

    dmaConfigCtrlPacket((uint32)(&TX_DATA),(uint32)(phetREG1DOUT8),2);

    dmaSetCtrlPacket(DMA_CH0,g_dmaCTRLPKT);

    dmaSetChEnable(DMA_CH0, DMA_HW);

    dmaEnableInterrupt(DMA_CH0, BTC);

    dmaEnable();



    /* Enable IRQ - Clear I flag in CPS register */
    /* Note: This is usually done by the OS or in an svc dispatcher */


    hetInit();

    hetREG2->HRSH &= 0xFFFF0000;
    hetREG2->AND &= 0xFFFF0000;
    hetREG2->XOR &= 0xFFFF0000;


    hetREG2->REQENS = (hetREG2->REQENS & 0xFFFFFF00) | ((uint32_t)(1 << DMA_CH6));
    hetREG2->REQDS = (hetREG2->REQDS & 0xFF00FF00) | ((uint32_t) (1 << DMA_CH6));

    /* Run forever */

        /* CORTEX request signal pin - HIGH / LOW */
    hetREG2->DIR |= (1 << PIN_HET_0);
    hetREG2->DIR |= (0 << PIN_HET_4);
    hetREG2->DIR |= (1 << PIN_HET_6);
    hetREG1->DIR |= (1 << PIN_HET_24);
    hetREG1->DIR |= (1 << PIN_HET_25);
    hetREG1->DIR |= (1 << PIN_HET_26);
    hetREG1->DIR |= (1 << PIN_HET_27);
    hetREG1->DIR |= (1 << PIN_HET_28);
    hetREG1->DIR |= (1 << PIN_HET_29);
    hetREG1->DIR |= (1 << PIN_HET_30);
    hetREG1->DIR |= (1 << PIN_HET_31);

//    hetRAM2->Instruction[pHET_L00_0].Data = (hetRAM2->Instruction[pHET_L00_0].Data & 0x0000007F) | ((uint32_t) 0 << 7);

    hetRAM2->Instruction[pHET_L06_0].Control |= ((uint32_t) 0x1 << 27); // gen request

    hetRAM2->Instruction[pHET_L09_0].Data = (hetRAM2->Instruction[pHET_L09_0].Data & 0x0000007F) | ((uint32_t) 24 << 7); //number of bytes

    hetRAM2->Instruction[pHET_L09_0].Control |= ((uint32_t) 0x1 << 0); //IRQ ON

    hetREG2->INTENAS |=  (1<<pHET_L09_0);

    while(1)
    {
        delay();

        hetRAM2->Instruction[pHET_L00_0].Data = (hetRAM2->Instruction[pHET_L00_0].Data & 0x0000007F) | ((uint32_t) 0 << 7);
    }

/* USER CODE END */

    return 0;
}


/* USER CODE BEGIN (4) */
void dmaConfigCtrlPacket(uint32 sadd,uint32 dadd,uint32 dsize)
{
  g_dmaCTRLPKT.SADD      = sadd;              /* source address             */
  g_dmaCTRLPKT.DADD      = dadd;              /* destination  address       */
  g_dmaCTRLPKT.CHCTRL    = 0;                 /* channel control            */
  g_dmaCTRLPKT.FRCNT     = dsize;                 /* frame count                */
  g_dmaCTRLPKT.ELCNT     = 1;             /* element count              */
  g_dmaCTRLPKT.ELDOFFSET = 4;                 /* element destination offset */
  g_dmaCTRLPKT.ELSOFFSET = 0;                 /* element destination offset */
  g_dmaCTRLPKT.FRDOFFSET = 0;                 /* frame destination offset   */
  g_dmaCTRLPKT.FRSOFFSET = 0;                 /* frame destination offset   */
  g_dmaCTRLPKT.PORTASGN  = 4;                 /* port b                     */
  g_dmaCTRLPKT.RDSIZE    = ACCESS_8_BIT;     /* read size                  */
  g_dmaCTRLPKT.WRSIZE    = ACCESS_8_BIT;     /* write size                 */
  g_dmaCTRLPKT.TTYPE     = FRAME_TRANSFER ;   /* transfer type              */
  g_dmaCTRLPKT.ADDMODERD = ADDR_INC1;         /* address mode read          */
  g_dmaCTRLPKT.ADDMODEWR = ADDR_OFFSET;       /* address mode write         */
  g_dmaCTRLPKT.AUTOINIT  = AUTOINIT_ON;       /* autoinit                   */
}
void delay()
{
    int i=0;
    for(i=0;i<500;i++)
    {
        asm(" nop ");

    }
}

void hetNotification(hetBASE_t *het, uint32 offset)
{
    hetREG1 -> DOUT = 0x0;
}

void createTxDummyPacket(uint8_t *packet, uint32_t size)
{
    uint32_t i = 0;

    for(i = 0; i < size; i++)
    {
        packet[i] = (i % 256);
    }
}
/* USER CODE END */

The folllowing code is the main.c file in the system.
Thank you

Hi Nuno,

Can you please check below thread once, it might helpful for your issue:

(+) TMS570LS1114: , ECAP IRQ cannot enter again. - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

--

Thanks & regards,
Jagadish.

it was kinda helpfull but i have a few questions. the method described the the thread didnt fix my issue since i dont have the respective module initialized ( module that enabels ecap)

Hi Nuno,

Please follow this sequence for performing VIM RAM parity selftest:

1. disable parity checking

2. disable the interrupt. 

3. initialize the VIM RAM using the hardware init mechanism

4. run the VIM parity check

5. After the selftest, please revert the flipped bit in VIM RAM back.

how do i do that?

is this in the driver sys_startup.c?

Yes, It is in sys_startup.c. 

You can use the same test sequence in main() or other files.