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MSPM0G3507: How to flush cache and prefetch logic?

William Toohey
Prodigy 50 points
Part Number: MSPM0G3507

In the TRM "6.3.3.5 Executing a PROGRAM Operation", the last step mentions:

Following programming of the flash memory, it is possible that there may be stale data in the processor's
cache and prefetch logic. Before reading locations which were programmed, it is recommended to first flush
the cache in the CPU subsystem.

How is this done? I tried clearing the ICACHE and PREFETCH bits in CPUSS.CTL after programming flash, but it appears I still get stale data (as a byte-by-byte memory check fails, but succeeds if run a second time).

  • +1
    TI__Mastermind 23065 points

    Hi William

    ICACHE.CTL register is Used to enable/disable Instruction caching on flash access.

    PREFETCH.CTL register is Used to enable/disable instruction prefetch to Flash

    Could you please clear these 2 register bits and enable them? 

    at the same time, could you please explain on the operation of (as a byte-by-byte memory check fails, but succeeds if run a second time)?

    Thanks

  • 0 in reply to Xiaodong LI
    Prodigy 50 points

    Ah, so clearing the bits is enough to clear the cache (and re-enabling them will start with an empty cache again)?

    If this is the case, then I must have a problem with my flash verify step - I will investigate further. Thank you for the clarification.