Hello Champs,
Customer is configuring MMCSD to SDIO mode, 4Bit data width, using CMD53 to read/write data, enable DATA_CRC interrupt. The slave device sends fewer data and MMCSD receives more data in order to generate the CRC error, but the DATA_CRC error in pReg->ERROR_INTR_STS can't be detected.
If using MMCSD1_DATA_PORT to read/write, the DATA_CRC can be detected. If using DMA mode, the DATA_CRC can't be detected.
SDIO_halNormalIntrSigEnable(sdioAttrs->ctrlBaseAddr,0xffff);
SDIO_halNormalIntrStatusEnable(sdioAttrs->ctrlBaseAddr,0xffff);
SDIO_halErrorIntrSigEnable(sdioAttrs->ctrlBaseAddr,0xffff);
SDIO_halErrorIntrStatusEnable(sdioAttrs->ctrlBaseAddr,0xffff);
const CSL_mmc_ctlcfgRegs *pReg = (const CSL_mmc_ctlcfgRegs *)(sdioAttrs->ctrlBaseAddr);
// Clear transfer mode and command registers
CSL_REG16_WR(&pReg->TRANSFER_MODE, 0U);
CSL_REG16_WR(&pReg->TIMEOUT_CONTROL, 0x02U);
CSL_REG16_FINS(&pReg->TRANSFER_MODE, MMC_CTLCFG_TRANSFER_MODE_RESP_TYPE, CSL_MMC_CTLCFG_TRANSFER_MODE_RESP_TYPE_VAL_R5);
CSL_REG16_FINS(&pReg->TRANSFER_MODE, MMC_CTLCFG_TRANSFER_MODE_RESP_INTR_DIS, CSL_MMC_CTLCFG_TRANSFER_MODE_RESP_INTR_DIS_VAL_DISABLE);
CSL_REG16_FINS(&pReg->TRANSFER_MODE, MMC_CTLCFG_TRANSFER_MODE_RESP_ERR_CHK_ENA, CSL_MMC_CTLCFG_TRANSFER_MODE_RESP_ERR_CHK_ENA_VAL_ENABLE);
CSL_REG16_FINS(&pReg->TRANSFER_MODE, MMC_CTLCFG_TRANSFER_MODE_DMA_ENA, 1);
// CSL_REG64_FINS(&pReg->CAPABILITIES, MMC_CTLCFG_CAPABILITIES_SDMA_SUPPORT, 1);
CSL_REG16_FINS(&pReg->HOST_CONTROL2, MMC_CTLCFG_HOST_CONTROL2_HOST_VER40_ENA, 0);
CSL_REG8_FINS(&pReg->HOST_CONTROL1, MMC_CTLCFG_HOST_CONTROL1_DMA_SELECT, 0); //0-SDMA
CSL_REG16_FINS(&pReg->BLOCK_SIZE, MMC_CTLCFG_BLOCK_SIZE_SDMA_BUF_SIZE, 0); //0-4KB
Thanks
Regards
Shine
