Part Number: LP-MSPM0G3507
HI Champs,
Customer needs CLK_OUT with the output clock frequency of 4915200 Hz.
Is it possible to achieve this setting on the lanuchpad?
How?
Thanks
Tamas
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Part Number: LP-MSPM0G3507
HI Champs,
Customer needs CLK_OUT with the output clock frequency of 4915200 Hz.
Is it possible to achieve this setting on the lanuchpad?
How?
Thanks
Tamas
Hi Tamas,
How accurate do they need to be on that frequency?
On the launchpad it looks to me that there is no way to generate this with the hardware as is. We'd need to use the SYSPLL to multiply one of the available input frequencies (HF Crystal or SYSOSC) to a common multiple with their desired frequency, and then divide it down. The least common multiple of 4915200 Hz and the 4MHz SYSOSC frequency is above 3GHz, which is outside the acceptable fVCO range for the SYSPLL.
There are ways to get close, for example, you could use a 4MHz SYSOSC with a predivider of 2, and a feedback divider of 49, to get an fvco of 98MHz, that could be divided down to 4.9MHz and sent to CLK_OUT. You could also potentially trim the SYSOSC to get close, but the knobs for trimming are around 100kHz (RFINE) and 1MHz (RCOARSE). To me it seems like you would be compromising on that nominal frequency a bit no matter what. This method might be the best option depending on how close to nominal they need to be.
On different hardware, you could use an external crystal that can be easily divided down to the 4915200 frequency. Depending on whether or not they planned to have an external crystal, adding one just to get this frequency out may or may not be worth it.
Best Regards,
Brandon Fisher