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EK-TM4C123GXL: The most efficient method to get samples from one adc channel via dma to memory

Kevin Hinrichs
Prodigy 180 points
Part Number: EK-TM4C123GXL

I looked at the example adc_udma_pingpong and have questions about it:
1. why do I need to enable burst mode on a channel with a sequence? Or in other words, what advantages does this give me?

//
// Set the USEBURST attribute for the uDMA ADC0 channel.  This will force
// the controller to always use a burst when transferring data from the
// TX buffer to the UART.  This is somewhat more efficient bus usage than
// the default which allows single or burst transfers.
//
uDMAChannelAttributeEnable(UDMA_CHANNEL_ADC0, UDMA_ATTR_USEBURST);

2. there is always a sample transmitted via dma. In the data sheet on page 801 I see a FIFO block with 4 cells. Can this be used to transfer 4 finished samples via dma?
Then the burst mode would make sense for me again.

3. on page 807 in the data sheet it is about hardware sample averaging. This 4 cell FiFo is also shown there. 4 samples are combined and divided by the number of samples. I am still unsure with which sample rate an averaged sample was sampled. I have the function; ADCClockConfigSet() and about ADCSequenceConfigure() I can set a timer with a fixed frequency. I think I need an example.

  • 0
    TI__Guru**** 191296 points
    Kevin Hinrichs said:

    1. why do I need to enable burst mode on a channel with a sequence? Or in other words, what advantages does this give me?

    First of all, you can only use burst for ADC transfer. Please see below. As you know there is a FIFO associated with a Sample Sequencer, a burst would allow uDMA to read all the available data in the FIFO in one shot instead of reading each data as an individual uDMA transaction. Take SS0 for example, the depth of the FIFO is 8. Why wouldn't you want to read all eight data at once. This is the advantage compared to reading in 8 different uDMA transactions. 

    Kevin Hinrichs said:
    2. there is always a sample transmitted via dma. In the data sheet on page 801 I see a FIFO block with 4 cells. Can this be used to transfer 4 finished samples via dma?
    Then the burst mode would make sense for me again.

    Yes, your understanding is correct. 

    Kevin Hinrichs said:
    3. on page 807 in the data sheet it is about hardware sample averaging. This 4 cell FiFo is also shown there. 4 samples are combined and divided by the number of samples. I am still unsure with which sample rate an averaged sample was sampled. I have the function; ADCClockConfigSet() and about ADCSequenceConfigure() I can set a timer with a fixed frequency. I think I need an example.

    I'm not sure if your understanding is correct. Hardware Averaging is not to take samples of 4 channels and take the average of it. Of course, you could do too. Let's say you use SS1 where 4 channels can be sampled. On your board, you could route your analog ADC input to all 4 channels. In another word, all 4 channels are taking samples of the same input. Your application can do the averaging but that is a software approach of averaging. The ADC module has a hardware Sample Averaging Circuit. This is a hardware averaging.  Let's say for example you are using SS3. This sample sequencer can only take one sample on one input channel. You could still enable hardware averaging. For example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. In another word, the input will be taken 16 samples before the final average is moved to the FIFO. If an interrupt is enabled, the interrupt is not generated until 16 samples have been taken. 

  • 0 in reply to Charles Tsai
    Prodigy 180 points

    I would like to thank you again for the help here in the forum! I have never had a question not answered here.
    I still have a question about point 2.
    I need current only one analog input. For this reason I use the SS3, because I need only one sequence. This also means that only one sample is transported via dma.
    My question is, can I use the SS1 to optimize the dma transfer, so that always 4 samples are transferred?

  • +1 in reply to Kevin Hinrichs
    TI__Guru**** 191296 points
    Kevin Hinrichs said:
    My question is, can I use the SS1 to optimize the dma transfer, so that always 4 samples are transferred?

    Hi,

      How many analog inputs do you have if you were to use SS1? If you still have only one analog input then you will configure SS1 with only one step. After one sample is complete, it generates the DMA request. This does not help you much compared to using SS3. But you could route the one analog input to all four channels( or steps) in SS1. In this case, you could have DMA transfer all four data at once all four should have roughly the same conversion value. You could do some post processing of the data once they are moved by the DMA to the buffer. For example, you could take the average of four channels.