Other Parts Discussed in Thread: SYSCONFIG
Hello,
I'm using 2 HDSL connections: On on PRU0-CHannel1 (PRU0) and one on PRU1 Channel 0 (PRU-RTU 1). I'm using of course ICSSG0, compatible with the launch-pad I/O's.
The Channels are configured well and the channels are running calling them one channel at the time.
So far so good, but running both channels simultaneously, is not possible. One channel will shut down after some ms.
It is no EMI issue, because i made various tests, that moves the same wires, and I do not see an problem.
Going on further, it seems that the clock of the TX unit/Fifo is not independent from PRU-Slice-0 to PRU-Slice-1.
As soon i make a test Program running in place of on HDSL Channel and I swtich the Clock from FAST to NORMAL and to SLOW, the other
DSL Channel will go into fault. Transmitting instead data patterns with the fifo withut changing the clock,everything works.
Have anyone an Idea, how to overcome that problem and if my supposition that the Tx-Clocks are not independent is right ?
If it is so, the design of the PRU S/W is not siutable for multi-axis/Encoder Application and must be reviewed.
e.s. The Multi-channel define does not work at all, so I would prefere to have a design that is independent and does not foresee to much mixes.
Note: I interfaced the LP to my H/W (multiaxis (4) Drive/Encoder) which is using FPGA-IP for the HDSL's, so the H/W Setup is without doubt OK.
In advance, thanks to your kindly response.