As a follow up from the previous question: https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1228826/am2634-configure-uart-idle-line-interrupt
I confirm that it is actually possible to achieve Idle-line interrupt functionality on Sitara UART peripheral when using DMA to RX each byte of data. The interrupt used as "idle-line" is FIFO RX timeout
UART/DMA configuration to enable "idle-line interrupt" on top of the UART and DMA configuration :
UART_EFR2 -> TIMEOUT_BEHAVE = 1
UART_IER2-> RHR_IT_DIS = 1
One extra DMA transfer linked to UARTx_DMA1 (UART_RX event) that will take care of enabling UART_IER->RHR_IT as soon as the first byte is received from the UART peripheral.
On the interrupt handler side the interrupt generated is IT_TYPE_Value_6 | Rx timeout, and the handler has to clear UART_IER->RHR_IT, in order to prevent further interrupts to be generated, and eventually read back UART_IIR and clear the VIM to clear other pending interrupt that may have been already been pending (depending on the value in UART_TIMEOUTx, if/when used). Of course the handler or the DMA chaining have to be set up again the DMA transfers for the next UART RX frame.
