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AM2732-Q1: Would lockstep, parity, ECC feature influent the normal process

Andy Yin
Genius 9390 points
Part Number: AM2732-Q1

Hi,

If enable lockstep, parity, ECC, ECC bus safety feature, would those introduce any additional loading to the system?

My customer is doing FUSA, integrate all the above SM into their system, found the process output would sometime be abnormal, if disable the SM then it would work well all the time. 

Look forward to your comments.

ANDY

THANKS.

  • 0
    TI__Expert 8630 points

    Hi,

    AM273x supports 

    The device includes different modules for functional safety requirements support:

    • Logic BIST mechanism for all the CPU cores

    • PBIST mechanism for all the memories

    • ECC on the critical memories

    • MPU on all critical shared resources – MMRs and memories

    • Voltage monitor on all the primary supplies with >90% DC

    • Clock monitors to monitor all the primary clocks. At least one Watchdog per each subsystem.

    • PLL Lock monitors – PHASELOCK, FREQLOCK

    • Temperature sensors with an accuracy of +/-5°C near DSP, R5F, HSM, and all other temperature sensitive locations.

    • Separate safety island (MCU) with Lock-Step/Dual-Core Cortex-R5F.

    • Safety enabled interconnect

    • Two Error Signaling Modules (ESM) to enable error monitoring, 1 each in DSS and MSS.

    • Temperature monitoring sensors

    • Dedicated hardware Memory Cyclic Redundancy Check (MCRC) blocks.  

    To detect the faults in the system and handle that fault accordingly, above safety functionalities could be implemented. Enabling these should not load the CPU such that CPU would fail/behave abnormally.

    It could be because of something else. Could you please help with more details like when you say CPU behaves abnormally what doe s that mean ? 

    Does it crash ? Does it hang ? Do you have dump of registers when this happens ?

    Best Regards, Shiv