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AM2432: Is it possible to use both L1 Cache and TCM simultaneously on R5FSS on AM243x ?

Hideaki Matsumoto
Genius 9150 points
Part Number: AM2432

Hi,

Is it possible to use both L1 Cache and TCM simultaneously on R5FSS on AM243x ?

If it's possible, both memory can be accessed with no wait (800MHz) from R5F core in case of no cache miss, correct ?

Is this general use case ?

Regards,

Hideaki

  • 0
    TI__Expert 8630 points

    Hi Hideaki,

    Yes should be able to use L1 Cache and TCM simultaneously. Please note that the TCM size would differ in case of Lockstep/Dual core mode operation. Please refer to Notes in the section 1.3.1 and  R5FSS. 

    While I check and comeback on L1/TCM access by R5F in case of no cache miss, following benchmark app note might be helpful :

    https://www.ti.com/lit/an/spracv1a/spracv1a.pdf  section 3.1.3 Cortex-R5 Memory Access Latency.

    Best Regards, Shiv

  • +1 in reply to Shivasharan Nagalikar
    TI__Guru 55285 points

    Hi Hideaki-san,

    The L1 cache is for the memory other can TCM, such as OCRAM, DDR etc. It is dictated in the MPU settings in example.syscfg (if the "Region Attributes" in MPU ARMv7 of a memory region is set to ""Cached"). As of the TCM, it is not connected to the L1 cache, since it can be accessed by R5F cores in "no wait" (1.25ns). L1 cache can also be accesed by R5F cores in "no wait" (1.25ns), if it is a cache hit.

    Best regards,

    Ming