Part Number: MCU-PLUS-SDK-AM243X
Other Parts Discussed in Thread: SYSCONFIG
I'm building a project with all R5 cores and the M4 core. I've set up shared memory in the linker for each core, set up the MPU regions, and added a RAT entry on the M4 core as per the instructions in the linker file to enable it to access shared memory space.
If the R4 applications make a change to a region of shared memory, it 'propagates' (I know, it's supposed to all be the same memory) to all the other cores, including the M4 core. But, when I make a change using the M4 core, the memory changes only for the M4 core - the R5 cores don't see any change.
I can also observe this by manually modifying memory via the Memory Browser in debug, also. After initialisation across all cores, I pause them and change a location of shared memory on an R5 core. I can see the change with the memory browser watching the M4 core at the same memory location. But when I try the reverse, the memory browser shows the update when looking at the M4 core, but the R5 cores show no change.
This seems bizarre to me given that:
1. I've disabled caching in for the MPU region in Sysconfig and confirmed it in ti_dpl_config.c for each of the cores
2. This is supposed to physically be the same location in memory, so I'm unsure how it's showing two different states
Does anyone have anidea on how I might rectify this one-way shared memory?
Linker:
/* shared memories that are used by all cores */
/* On M4F,
* - By default MSMC RAM is not accessible to M4F, a RAT entry is needed to make it
* accessible on M4F
* - So make sure there is a RAT entry which has a 1:1 mapping from 0x70000000 to 0x70200000
*/
USER_SHM_MEM : ORIGIN = 0x701D0000, LENGTH = 0x00010000
RAT config:
{
.localAddr = 0x70000000u,
.systemAddr = 0x70000000u,
.size = AddrTranslateP_RegionSize_256M,
},
MPU config:
{
.baseAddr = 0x701D0000u,
.size = MpuP_RegionSize_16K,
.attrs = {
.isEnable = 1,
.isCacheable = 0,
.isBufferable = 0,
.isSharable = 1,
.isExecuteNever = 1,
.tex = 1,
.accessPerm = MpuP_AP_ALL_RW,
.subregionDisableMask = 0x0u
},
},
