Hello,
I am currently seeking an explanation as to what the "FMC - uncorrectable error (address parity on bus1 accesses)" - (ESM G2 CH4) - refers to?
Chapter 5 of the TRM does not appear to make any direct reference to parity functionality (in comparison to chapter 6, TCRAM). The only references to "parity" are as follows:
- Pg 254 within the ECC encoding table. My interpretation of this is that "even" or "odd" schemes are defined by the row, and impact the associated ECC bit by potentially adding an extra XOR operation. This is not a safety feature but rather pertains to the ECC encoding scheme.
- Pg 297 within the FPAR_OVR register overview. BUS_PAR_DIS notes that "address bus parity error and buffer parity error" can be disabled, indicating the presence of a safety feature that is enabled upon reset.
Would it be possible to provide an explanation of the safety feature being referenced within the FPAR_OVR register overview, as well as the condition that would result in an ESM G2 CH4 error? Additionally, would it be possible to define the referenced SYS_ODD_PARITY signal? This appears to be related to the parity safety feature, however, it is not defined within the TRM.
Thanks,
Grayson
