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MSPM0C1104: NONMAIN BCR memory configuration

Munan Xu
Expert 4940 points
Part Number: MSPM0C1104
Other Parts Discussed in Thread: UNIFLASH

Hello,

I have a customer who pointed out that there are some inconsistencies in the NONMAIN area and the boot configuration region. First it seems like the BCR configuration and its CRC overlap in terms of end address and start address. And it also looks like the CRC is only 1 byte:

Second the NONMAIN registers section describes this same address space as the BCRCONFIGID and then also does not leave room for the CRC:

One other thing I also see in the table above is that SWPMAINLOW and SWPMAINHIGH have the same description and also covers a region that's outside of the 16 kB of flash that's on the C1104.

Can someone provide a description of the actual NONMAIN memory region and the BCR config?

Munan

  • 0
    TI__Mastermind 29105 points

    Hey Munan,

    I think this might just misread.  I'll admit, I misread it too when looking at this E2E with your highlighting.  I think the 'B' at the end of the BCR address is just being ignored in our minds.  

    For Table 1-4:

    BCR is from 0x41C0 0000 to 0x41C0 005B   - 92 bytes

    BCR CRC is from 0x41C0 005C until 0x41C0 005F - 4 bytes  

    Then Table 1-7 just describes the register that live in the first 20 bytes of the BCR section.  

    I will provide the feedback on the SWPLow and High descriptions to make sure they get updated.  

    Thanks,

    JD

    Edit:  No CRC on M0C devices

  • 0 in reply to JD Crutchfield
    TI__Expert 4940 points

    Hey JD,

    When the CRC is calculated on the region does BCR cover the entire region from 41C00000 to 41C0005B? or does it only cover the region described in the TRM?

    Munan

  • 0 in reply to Munan Xu
    TI__Mastermind 29105 points

    Hey Munan,

    My understanding is that it's just on the entire memory space.  I don't have an M0C LP with me currently, but I can quickly test on an M0L.  

    Thanks,

    JD

  • 0 in reply to JD Crutchfield
    TI__Mastermind 29105 points

    Hey Munan,

    Atleast when programming an M0L, the entire memory section is checked.  I took a hex file that programs BCR and changed the 2nd to last byte and got an Corruption error in uniflash.  (This is how I've seen these CRC errors present during programming.)  

    Thanks,

    JD

  • 0 in reply to JD Crutchfield
    TI__Expert 4940 points

    Hey JD,

    So I think part of the confusion here is also if you compare the TRM from MSPM0L to MSPM0C there are substantial differences in the NONMAIN memory configuration.

    The L series, it's clearly marked what's APPCRC and BOOTCFGCRC and BSLCRC. In the M0C TRM it isn't clear in the register map where those crc values are and subsequently what they actually cover. So can we confirm what the BCRCRC actually covers and also where exactly it is in the NONMAIN memory section? And is there anything else in NONMAIN customer needs to be aware of?

  • 0 in reply to Munan Xu
    TI__Mastermind 29105 points

    Hey Munan,

    I believe it's as simple as BCRCRC resides at 0x41C0.005C-0x41C0.005F and covers the entire BCR NONMAIN memory region.  (0x41C0.0000 - 0x41C0.005B).  As for the space in NONMAIN that isn't defined by registers in M0Cx family, I would treat it as Reserved memory.  

    I will send your feedback about the BCRCRC being removed from the NONMAIN table to the systems team and ask to have it put back in with its description.    

    Thanks,

    JD

  • 0 in reply to JD Crutchfield
    TI__Expert 4940 points

    Hey JD,

    Thanks for the confirmation and for providing the feedback.

    Munan

  • 0 in reply to Munan Xu
    TI__Mastermind 29105 points

    Hey Munan,

    So, unfortunately, I was wrong on this one. I've confirmed with the Systems team, and the NONMAIN registers table is correct.  There is actually no BCR CRC in MSPM0Cxx devices.

    I've submitted a ticket with the team to update table 1-4 to remove the BCR CRC region and to remove section 1.4.1.1 that discusses CRC.  These are apparently legacy remnants from M0L/M0G TRM.  

    Thanks,

    JD