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AM2432: 2 questions for interrupt

Joyce Gao
Expert 3200 points

Part Number: AM2432

Hi expert,

Customer is evaluating LP-AM2432. Here are 2 questions:

1. Frequency is mentioned as 800MHz, but the control interrupt execution time is ~30us, which is close to F2837x. But F2837x is 200MHz frequency, meaning that in AM243x the excution time should be shorter than F2837x. Why's that? Is it because actually 1 R5F core is ~200MHz frequency and the interrupt runs in 1 R5F core?

2. In the example of enet_cpsw_fast_stattup, many interrupts are enabled. We also enabled a PWM interrupt in our motor control. But the real-time performance of our PWM interrupt is relatively poor. Setting the interrupt to 125us, then the interrupt period will fluctuate between 110-140us. In F28x, if only 1 PWM interrupt is set, then the fluctuation is shorter than 1us. Why's that and how to improve?

Many thanks!

Joyce

  • 0
    TI__Expert 3200 points

    Hi expert,

    Additional for the 2nd question, could you maybe help provide EtherNet driver without any interrupts for customer to test?

    Joyce

  • 0 in reply to Joyce Gao
    TI__Expert 3200 points

    Hi expert,

    Could you please help see this case? Many thanks!

    Joyce

  • 0 in reply to Joyce Gao
    TI__Mastermind 26195 points

    Hi Joyce,

    I am getting more information on the architecture of the device to get more information.

    Best Regards,
    Aakash

  • 0 in reply to Aakash Kedia
    TI__Expert 3200 points

    Hi Aakash,

    Any updates?

  • 0 in reply to Joyce Gao
    TI__Expert 7835 points

    Hi Joyce,

    The two concerns reported by customer are mainly related to ISR response time and preemption of AM243x. I am working with software team to come up with some optimization suggestions to help resolve the concerns.

    In short answer, C2000 will take less CPU clock cycle to enter an ISR, especially when enabling FPU, because it have less registers to save when switching context. So although AM243x have a higher clock frequency, it will not have 4x improvement that customer is expecting in terms of ISR response time. But we will be able to improve from their current performance with software optimization suggestions. 

    Please allow us some time to come up with suggestions. Thanks.

    Han

  • 0
    TI__Guru 57005 points

    Hi Joyce,

    There are many things can affect the performance of R5F cores. Here are a few:

    1. Are you suing the release version (typically -o3) for your application code.

    2. Where did you put your application code and data? There are 128KB TCM for each R5F cluster. The TCM is single cycle wait time memory. The On Chip memory on the other handle is relative slow. The rule of thumb is to put the time critical code and data in the TCM.

    3. You said you are running motor control and the enet_cpsw_fast_stattup example. Are they running on different R5F cores or they are all running on the same R5F core? 

    4, The on-chip memory is in 256KB blocks (8 of them). Try to put the code and data for different R5F cores into different blocks. It can also improve the performance.

    Would you mind describe the system architecture of your application in details and is it possible to send the linker.cmd and the map file?

    Best regards,

    Ming