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AM2434: DDR4 Mode Register Configuration Issue

Daisuke Maeda
Guru 20285 points
Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

When our customer checked the mode register settings using an analyzer during the DDR4 initialization phase, the value of A12:A10 in "Mode Register 6 (MR6)" showed 011b, but 011b means data rate not supported by AM2434.

Our customer includes and uses a header file "board_ddrReginit.h" generated using the "DDR Subsystem Register Configuration" in the Sysconfig tool. The value of bits 12:10 of the register corresponding to the data to program into MR6 in the header file showed 001b.

0x00000493U, // DDRSS_CTL_242_VAL
0x00000493U, // DDRSS_CTL_243_VAL
0x00000493U, // DDRSS_CTL_244_VAL
0x00000493U, // DDRSS_CTL_245_VAL
0x00000493U, // DDRSS_CTL_246_VAL
0x00000493U, // DDRSS_CTL_247_VAL

I understand that to set MR6 in the initialization phase, these values in the header file are set in the registers below, and the values are reflected as they are, is that correct?

AM64x/AM243x Technical Reference Manual (Rev. G)
8.1.5.293 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_242 Registers (Page 4492)
8.1.5.294 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_243 Registers (Page 4493)
8.1.5.295 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_244 Registers (Page 4494)
8.1.5.296 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_245 Registers (Page 4495)
8.1.5.297 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_246 Registers (Page 4496)
8.1.5.298 CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_247 Registers (Page 4497)

Why was MR6 set to a different value than in the header file?

Can the MR6 settings be changed by training during the initialization phase?

Best regards,

Daisuke

  • 0
    TI__Guru 55905 points

    Hi Daisuke,

    I am not seeing the incorrect MR6 for our AM243x EVM. Here is the CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_242 to 247 Registers view after the SBL_NULL which runs the DDR_init also for AM243x EVM.

    Here is the CTLPHY_WRAP__CTL_CFG__CTLCFG_DDR16SS_DENALI_CTL_242 to 247 Registers view after the System_init  --> DDR_init() which applies gDdrParams.DDRSS_ctlReg to DDRSS_ctlRegNum:

    As you can see the MR6 was set properly in both cases.

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    Guru 20285 points

    Hi Ming-san,

    Thank you for your repry.

    Daisuke Maeda said:
    When our customer checked the mode register settings using an analyzer during the DDR4 initialization phase, the value of A12:A10 in "Mode Register 6 (MR6)" showed 011b, but 011b means data rate not supported by AM2434

    Our customer has confirmed that the values in the registers are correct. However, when they use an analyzer to check the output signals during the initialization phase, the MR6 shows a different value than the values in the registers.

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Guru 55905 points

    Daisuke-san,

    I checked with our DDR expert on the MR6 value sent to DDR module during the initialization. It should be 

     0x00000493U, // DDRSS_PI_303_VAL instead of 

    0x00000493U, // DDRSS_CTL_242_VAL in board_ddrReginit.h

    However, both items show value of 0x493 in memory browser, so it does not solve your problem. 

    Is it possible for your customer to provide the analyzer dump for further investigation?

    Best regards,

    Ming