• State Resolved
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 3 replies
  • Subscribers 31 subscribers
  • Views 319 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

MSPM0G1507: More information about VREF Sample and hold mode

rperezti
Genius 12670 points
Part Number: MSPM0G1507
Other Parts Discussed in Thread: SYSCONFIG

We need information about the sample and hold feature of the VREF module. When and how does one configure and use this feature? The MSPM0G Series TRM Section 15.1 has a single bullet that states "Sample and hold mode supports VREF operation down to STANDBY operating mode". There are also a few register bit fields described in Section 15.3 that seem to be related to this (SHMODE, RATIO, HCYCLE, SHCYCLE) but there is not enough information to explain the purpose of this feature or how to use it. We looked in the TRM and datasheet but we could not locate additional information about this. Is there additional documentation or examples that we can reference to understand this feature better?

Thanks in advance

  • 0
    TI__Mastermind 28075 points

    Hi Ruben,

    I agree we don't seem to have anything available that describes this mode yet. Looking into this for you to see if we have a description internally anywhere of how this actually works.

    Just to provide some info, SysConfig does have brief descriptions for the SHCYCLE and HCYCLE Settings:

    SHCYCLE:

        The recommended sample time is >30us waiting for VREF to stabilize.

    The timing is calculated as:

            Sample_time =Sample_cycles/VREF_Clock

            Where:
                VREF_Clock = VREF_Clock_Source/VREF_Clock_Divider
                (See Clock Configuration section for more details).

                Sample_cycles = 0 to 65535.

            If VREF_Clock is 32.768kHz (i.e. LFCLK), and Sample_cycles = 1, the resulting Sample_time will be ~30.51us.

    HCYCLE:

        Hold time should be such that the accuracy degradation due to leakage is within
    DAC acceptable limits. The recommended hold time is 6ms.

    The timing is calculated as:

            Hold_time = Hold_cycles / VREF_Clock

            Where:
                VREF_Clock = VREF_Clock_Source/VREF_Clock_Divider
                (See Clock Configuration section for more details).

                Hold_cycles = 0 to 65535.

            If VREF_Clock is 32.768kHz (i.e. LFCLK), and Hold_cycles = 197, the resulting Sample_time will be ~6.01ms.

    Ratio is just setting the clock divider for VREF_Clock that these descriptions reference. 

    Best Regards,
    Brandon Fisher

  • +1 in reply to Brandon Fisher94
    TI__Mastermind 28075 points

    Hi Ruben,

    I didn't find an adequate description of this feature anywhere, so I've just tested it myself. As the name implies its just a sample and hold mode for the VREF circuit. It charges the external VREF capacitor during the "Sample" portion of the phase to the configured VREF Voltage. During the Hold Phase, the VREF capacitor is allowed to discharge as you would expect.

    Typically you want your sample time long enough and your hold time short enough that the VREF value does not dip too much. The value on the charged capacitor is the actually used reference value (see below for an example of this with a COMP, VREF+ is applied to COMP- and 1.3V DC is applied to COMP+). 

    This mode helps conserve power, and allows the VREF module to be periodically disconnected down into STANDBY0 and STANDBY1 (although this also works in higher power modes). 

    For register settings, SHCYCLE is the whole sample & hold cycle time (~1 Second in the above). So the total sample time is (SHCYCLE-HCYCLE)/VREF_Clock. Your hold time is HCYCLE/VREF_Clock. 

    Let me know if there are any more specific questions on this module. Adding information to the TRM to include more info on this mode has been added to a pending update. 

    Best Regards,
    Brandon Fisher

  • 0 in reply to Brandon Fisher94
    TI__Genius 12670 points

    Perfect thanks!