• State
  • Locked Locked
  • Replies 7 replies
  • Subscribers 31 subscribers
  • Views 438 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570 - Error detection/correction mechanisms

TMS570LS3137: Flash ECC no behaving as expected

Laurent Crochet
Prodigy 40 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi,

I'm working with a custom TMS570LS3137 board.

I enabled the Flash ECC and I'm trying to test it. To do so, I used the --ecc:data_error option of the linker. I also made the linker generate the ecc bits.

In CCS, I programed the flash with the 'Auto-ECC generation' disabled.

My first test concerns one single-bit error. The first time, it seemed to worked:

Error is visible in Memory window, the error is corrected when reaching that element and FCOR_ERR_ADD  & FCOR_ERR_POS are correct.

Could you confirm that this is how it should work?

I repeated the test and this time, not the same behavior. Error is corrected before reaching that line. Some times FCOR_ERR_ADD is correctly set, some times not.

I first thought Memory browser would compute it itself (on the computer) but it's not the case.

I also thought that looking at the Memory browser is also reading it from flash, than explaining why it is corrected sooner than expected.

I tried closing Disassembly and Memory windows, but it's still not correcting the error at the right moment.

I tried changing error location several times, still the same behavior. I also tried disabling Pipeline, unsuccessfully.

I enabled profiling and set threshold, not working as well.

I also noted that after reset, the corrected error re-appears.

I'm wondering the following points:

  1. is there a cache explaining what I see?
  2. is there a 'table' retaining previous errors, so that they would be corrected sooner?
  3. is the FCOR_ERR_ADD register reset when performing a System Reset with the debugger?
  4. do I have to enable profiling in flash wrapper?
  5. is the flash corrected/written when the ECC detects an error? Seems weird but reading the TRM, this is what I understand.

Furthermore, I wanted to enabled the related interrupt (through ESM), in case I should reset the error flag. I'm not able to do so.

I called the following (Halcogen default):

_coreEnableEventBusExport_();

    flashWREG->FEDACCTRL1 = 0x000A060AU;

    _coreEnableFlashEcc_();

I also enabled the ESM low level interrupt.

The interrupt is never entered.

Could you help me understand what I'm missing?

In advance, thanks

Laurent

  • 0
    TI__Guru*** 135355 points

    Hello Laurent,

    Our expert for this topic is out on local holiday and will be back on Wednesday, please wait for their feedback until then, thank you.

    Best Regards,

    Ralph Jacobi

  • 0 in reply to Ralph Jacobi
    TI__Guru 69891 points

    Hello Laurent,

    Apologies for the delay in my response, here in india we got couple of holidays.

    Now i started working on your issue, and will provide an update ASAP.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 69891 points

    Hello Laurent,

    Laurent Crochet said:
    Error is visible in Memory window, the error is corrected when reaching that element and FCOR_ERR_ADD  & FCOR_ERR_POS are correct.

    Yes, it is correct, the single bit errors will automatically get corrected.

    Laurent Crochet said:
    I repeated the test and this time, not the same behavior. Error is corrected before reaching that line. Some times FCOR_ERR_ADD is correctly set, some times not.

    What i am suspecting of this behavior is, the CPU itself will generate some random speculative fetches. And if it finds any location with invalid ECC then it will set corresponding ESM flags and registers.

    Refer below paragraph:

    --

    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 40 points

    Hi Jagadish,

    No worry for the delay.

    You're right, I haven't notice that part.

    Are speculative fetches due to 128-bit fetching even when only 32 bits are needed?

    But then, how could I test the ESM functionality? Till now, I was not able to get any ESM event from flash ECC. The interrupt are not enabled immediately after startup, hence if CPU does speculative fetches, I cannot test it.

    Best regards,

    Laurent

  • 0 in reply to Laurent Crochet
    TI__Guru 69891 points

    Hello Laurent,

    It is not possible to disable the speculative fetches by the processor.

    If you want to test the ESM flags then you can use the Flash Diagnostic registers.

    To understand how to generate the corresponding errors, please refer SDL(Safe Diagnostic Library) code.

    For example, here is the code for to generate the ESM for FMC uncorrectable error:

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 40 points

    Hello Jagadish,

    Thanks for the reply, I will try it soon.

    Could you still clarify these points:

    • do I have to enable profiling in flash wrapper?
    • is the flash corrected when the ECC detects an error? I mean, if I get an error correction and I power reset the board, will the error appear again or is it vanished?

    Regards,

    Laurent

  • 0 in reply to Laurent Crochet
    TI__Guru 69891 points

    Hi Laurent,

    Laurent Crochet said:
    do I have to enable profiling in flash wrapper?

    No need to enable the profiling, please refer the diagnostic code.

    Laurent Crochet said:
    is the flash corrected when the ECC detects an error? I mean, if I get an error correction and I power reset the board, will the error appear again or is it vanished?

    Yes, the error appears again. The ESM flags will not get reset after power reset.

    --

    Thanks & regards,
    Jagadish.