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TM4C1299NCZAD: Communication interface between TM4C and FPGA to control memory mapped by Quad-SSI

Kenley
Intellectual 1755 points
Part Number: TM4C1299NCZAD

Hi team,

My customer is considering TM4C1299NCZAD with our new design board.
They are considering TM4C1299NCZAD for their new design board.
They are studying whether it is possible to use EPI or Quad-SSI for communication interface between TI microcontroller and FPGA to control memory mapped,

■ Questions
1) Is memory mapped control possible with Quad-SSI?

2) According to the data sheet, it seems that EPI can set 8/16/32-bit parallel bus.
What is the number of IO used for EPI 8-bit, 16-bit, and 32-bit? (Sorry, I checked the datasheet, but I didn't really understand how to read it.)

The communication format and the number of IO will change depending on the option settings such as SDRAM and SRAM,

but they are considering EPI 8bit to reduce the number of IO while providing high-speed access.

  • +1
    TI__Guru**** 191486 points
    Kenley said:

    1) Is memory mapped control possible with Quad-SSI?

    Hi,

      The question is no. QSSI can operate as a parallel SPI or a legacy SPI mode only.  

    Kenley said:
    2) According to the data sheet, it seems that EPI can set 8/16/32-bit parallel bus.
    What is the number of IO used for EPI 8-bit, 16-bit, and 32-bit? (Sorry, I checked the datasheet, but I didn't really understand how to read it.)

    General Purpose mode is the mode to use for interfacing with FPGA. The number of I/Os depends on the number of addresses you need. Refer to the table in your device specific datasheet. A maximum number of 32 I/Os are used. For example, if your data width is 8 bits then you can have up to 20 bits of addresses. If you don't need 20 bits of addresses to interface with the FPGA then your number of I/Os needed will be less. Let's say you only need to 8 address bits and 8 data bits and you if you need 4 bits for control (WR, RD, Frame, CLK)  then the number of I/Os needed will be 20. 

  • 0 in reply to Charles Tsai
    TI__Intellectual 1755 points

    Hi Charles,

    Thank you for the prompt reply!

    Let me confirm the following, is my understanding correct?

    ■ General purpose Mode:
    The frame signal allows the address and data to be 8-bit signal lines, even if it is A16 or D16-bit work of the other FPGA.
    Memory map control of A16 and D16 is possible by setting FrameCount = 1 and setting it to one frame with two accesses
    However, it only supports one-to-one connections.

    ■ Host bus mode:

    It is possible to communicate with multiple threads (cs) of one-to-many, but frame control is not possible.

    And if the data of the destination FPGA is 16 bits, the CPU can be set to 12, 16 bits, 32 IO.

    Best regards,

    Kenley

  • 0 in reply to Kenley
    TI__Guru**** 191486 points

    Hi,

      Please refer to the datasheet description about FRAME signal. 

    FRAME Signal Operation
    The operation of the FRAME signal is controlled by the FRMCNT and FRM50 bits. When FRM50 is
    clear, the FRAME signal is high whenever the WR or RD strobe is high. When FRMCNT is clear, the
    FRAME signal is simply the logical OR of the WR and RD strobes so the FRAME signal is high during
    every read or write access,

    Also refer to the Host Bus description where you can communicate via multiple CS signals. 

    I

    In Host Bus mode, you use CS, not FRAME signal. 

  • 0 in reply to Charles Tsai
    TI__Intellectual 1755 points

    Hi Charles,

    Thank you for the support.

    Sorry I just would like to confirm whether my understanding correct or not regarding the following.

    Did you mean that my understanding is not correct ?

    ■ General purpose Mode:
    The frame signal allows the address and data to be 8-bit signal lines, even if it is A16 or D16-bit work of the other FPGA.
    Memory map control of A16 and D16 is possible by setting FRMCNT = 1 and setting it to one frame with two accesses
    However, it only supports one-to-one connections.

    ■ Host bus mode:

    It is possible to communicate with multiple threads (CS) of one-to-many, but frame control is not possible.
    And if the data of the destination FPGA is 16 bits, the CPU can be set to 12, 16 bits, 32 IO.

    Thank you in advance.

    Best regards,

    Kenley

  • 0 in reply to Kenley
    TI__Guru**** 191486 points
    Kenley said:
    The frame signal allows the address and data to be 8-bit signal lines, even if it is A16 or D16-bit work of the other FPGA.
    Memory map control of A16 and D16 is possible by setting FRMCNT = 1 and setting it to one frame with two accesses
    However, it only supports one-to-one connections.

    Hi,

      Let's first make sure we are on the same page when we talk about A16 or D16. Please refer to the below table heading. Let's look at the second column first. It says D8 and A20. D8 means 8 bits of data and A20 means 20 bits of address lines. What this column is showing is that if you have 8 bits of data, then you can have up to 20 bits of address lines. Lookin at the 3rd column, it says D16, A12. This means 16 bits of data and 12 bits of address lines. In another word, if your FPGA needs 16 bits of data then you are limited to only 12 bits of address. You cant have 16 bits of data and 16 bits of address. 

    Kenley said:

    ■ Host bus mode:

    It is possible to communicate with multiple threads (CS) of one-to-many, but frame control is not possible.
    And if the data of the destination FPGA is 16 bits, the CPU can be set to 12, 16 bits, 32 IO.

    In host-bus mode, you don't use FRAME signal. You use CS signals. If you look at the tables for EPI Host-Bus 16 Signal Connections or EPI Host-Bus 8 Signal Connections, there is no FRAME signal. The CS signals is used for frame control if that is what you mean. 

    If you need 16 bits of data in Host Bus Mode then you can configure in various modes that allow you to have a maximum of 28 bits of address signals to support up to 512MB of memory space. If your FPGA only needs to 8 bits of address then you don't need all 32 bits of I/Os. 

  • 0 in reply to Charles Tsai
    TI__Intellectual 1755 points

    Hi Charles,

    Thank you for the explanation.

    Let me talk to customer based on your feedback.

    For the general purpose mode,

    So do you mean customer could not use it for 16 bits of data and 16 bits of address FPGA ?

    Is there any way to use for D16・A16 ?

    Thank you in advance.

    Best regards,

    Kenley

  • 0 in reply to Kenley
    TI__Guru**** 191486 points

    Hi Kenley,

      It is not possible to use 16 bits of data and 16 bits of address. Again please refer to the General Purpose mode signal connection table. Only 32 pins are used in General Purpose mode. For 16 bits of data, only 12 bits of address are available. You need other pins for WR, RD, Frame and Clock. 

  • 0 in reply to Charles Tsai
    TI__Intellectual 1755 points

    Hi Charles,

    Noted. Thanks!!!

    Regards,

    Kenley