RM57L843: Clocks before the PLL and clocks are configured

Hi Marcio,

After reset the device defaults to the clock on the OSCIN, that means it will directly operate with the crystal frequency.

Marcio Borges said:

Can watchdog be enabled before the systemInit() ? If yes, what is the value of RTICLK1? Does the watchdog needs to be reconfigured after systemInit()?

Different clock sources can be selected for RTICLK1 and even we can select OSC clock also for RTICLK.

So, according to this it should work before PLL also. 

but there is one condition to be met,

If clock source is other VCLK for RTI then RTI frequency must be less than VCLK/3. So please ensure to do that.

This is just theory but please try to test it in practical.

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Thanks & regards,
Jagadish.

Hello Jagadish,

Thanks for the responses.

My program is not doing the right thing. It configures the watchdog before calling errata_SSWF021_45_both_plls() and mapClocks(). If I am not wrong, looking at the RTI Clock Source Register (RCLKSRC), at this time, RTICLK is equal VCLK, which does not comply with the VCLK/3 rule.

I have observed that configuring the watchdog Texp with 128ms before calling errata_SSWF021_45_both_plls(), does not work. But setting Texp to 256ms, works.

Is VCLK after the reset iqual 75MHz?

Best regards,
Marcio.