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AM2432: What's the bandwidth of the shared OCRAM ?

Hideaki Matsumoto
Genius 9050 points
Part Number: AM2432

Hi,

Could you tell us what the bandwidth of the shared OCRAM ?  xx bit width?  xx MHz?

According to the following application note, we found that the Memory access latency of the shared on-chip SRAM is 63.75 ns (51 cycles).

https://www.ti.com/jp/lit/pdf/spracv1

I guess this latency is required at the first access only, not every bytes access.

Do you have any benchmark data of accessing from R5F to OCSRAM ?  xxxMB/s ?

What's the access time in the case of Read/Write 4 x 32bit data ?

Thanks and regards,
Hideaki

  • +1
    TI__Guru 54785 points

    Hi Hideaki-san,

    The actual bandwidth from R5F cores to/from shared OCRAM is very complicated to compute. The OCRAM and R5F core are connected via VBUS SCR which is 64b @ 250Mhz. There are 8 64b vbusm each connects to a 256KB bank. Those 8 64b vbusm can be access by different R5F cores at the same time. That makes the bandwidth hard to compute. Of course, the theoretical bandwidth for the OCRAM is 64*250Mhz*8 16GB/s.

    We do not have the benchmark data for R5F to/from OCRAM. We do have a STREAM for DDR4. If you can change the STREAM code for OCRAM, then you can get those benchmark data.

    The latency in spracv1 is for all the access from the OCRAM (as long as it is not in the cache)

    Since the VBUS SCR is 64b, so 2x32bit data access will have some advantages.

    Best regards,

    Ming