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Original question:

AM2432: SORTE_G device, TSK_IOEX_STATE_TTS_COMPLETE_EVENT processing

AM2432: Wait processing for sending packet gaps

hiroyasu-shimizu
Intellectual 490 points
Part Number: AM2432

［日本語］
　
ソースコードの赤枠で囲まれた(L896～L901)は、5usの待ち処理だと認識しています。
このコードと同じ方法でパケット間ギャップの待ち処理を構築しようと考えています。
この方法で何か懸念事項等はありますか？

［English］
　
The parts (L896 to L901) surrounded by a red frame in the source code are recognized as 5us waiting processing.
I'm thinking of building inter-packet gap waiting processing using the same method as this code.
Are there any concerns with this method?

  • 0
    TI__Mastermind 44834 points

    Hi,

    Thanks for your query, we will get back with a response by tomorrow.

  • 0
    TI__Expert 5230 points

    Hi Shimizu-san,

    There is no concern to implement a delay time like this. This is just like a NOP loop, that let's the PRU wait before going to the next software part.

    However, for IPG, the ICSS HW will make sure to automatically handle the IPG time once the TX_EOF command has been issued. This means that once the TX FIFO has been emptied from the last frame transmission, the IPG timer is active. When you push data into the TX FIFO for transmission of a new data frame, the IPG timer first needs to expire before the new transmission is started.

    The IPG timer delay can be configured via registers: see MII_RT_TX_IPG0.

    Regards,

     Thomas

  • 0 in reply to Thomas Mauer
    Intellectual 490 points

    ［日本語］
    >The IPG timer delay can be configured via registers: see

    それは、L194～L197がそれに該当するのでしょうか？

    ［English］
    >The IPG timer delay can be configured via registers: see

    Does that apply to L194 to L197?

  • 0 in reply to hiroyasu-shimizu
    TI__Expert 5230 points

    Yes, in this example the value of 0x18 is written into both registers. 

    The value must be given in units of 4ns cycle.

    • 0x18 * 4ns = 96ns IPG. This is the IPG used for Gbit Ethernet.

    Regards,

     Thomas