RAM Vs Flash

JR Simma

Martin, very good work. I'm having the same problem and with the same test. Since our tests were the same, would you mind sharing your conclusions?

Also, I have another question. My routine takes about 12 clock cycles longer when running from RAM. I would expect RAM timing to be better than flash. Is there any explanation why running linear code from RAM takes longer than flash?

Thanks,

JR Simma

Simma Software, Inc

The J1939 Experts

over 14 years ago

0 steveg over 14 years ago

Intellectual 270 points

Cortex supports a Harvard memory architecture, that is seperate data and instruction buses, if you run your code from RAM your effectively shutting down one of those paths, hence slower code.

0 JR Simma over 14 years ago in reply to steveg

Intellectual 660 points

Makes sense, thanks.

0 KGreb over 14 years ago in reply to steveg

TI__Mastermind 23000 points

Adding a slight clarification. There are three 64b TCM interfaces on the TMS570LS: ATCM (flash), B0TCM(SRAM), and B1TCM(SRAM). The B0TCM and B1TCM ports have the address decode interleaved on 64b boundaries. Assuming no DMA access, the only time you would see a performance loss when running from SRAM would be a cycle of delay on first point of arbitration; after that, the instruction/data accesses will interleave on the two SRAM TCM interfaces.

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RAM Vs Flash