• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 30 subscribers
  • Views 228 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LP-MSPM0G3507: Counting direction of PWM mode with SYSCFG

Alan
Prodigy 155 points
Part Number: LP-MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

I have configured a timer in PWM mode using SYSCFG, and am trying to understand what configuration it's setting up for me.  From the code in DL_Timer_initPWMMode(), I can see that a CENTER_ALIGNed timer is configured to set the output high when counting up and low when counting down (assuming I've interpreted (DL_TIMER_CC_CUACT_CCP_HIGH | DL_TIMER_CC_CDACT_CCP_LOW) correctly).  In my mind, this would be consistent with a counter in up-down mode, with the center-alignment applied to the center of the high-period. It also matches the drawn use-case in section 23.2.5.2.2 which demonstrates center-aligned PWM using up-down counting.

However, later in that function it looks like the CVAE bits in CTRCTL are being cleared, which the reference manual describes as operating in down-up mode, which I think would actually center-align about the low-period of the pulse.

Is the intention of the SYSCFG to set the PWM up in up-down mode or down-up mode when using SYSCFG in this way?

  • +1
    TI__Mastermind 28075 points

    Hi Alan,

    Looking at this your description of the behavior SYSCFG is defaulting to is correct.

    The actual PWM waveform generated is correct (based on frequency and duty cycle), but this does seem to be in Down-Up rather than Up-Down. Which would mean the center/zero of the Down-Up period occurs during a low pulse rather than a high one. Output wise, since everything is symmetric in this mode I don't believe it ends up mattering that much. Both the high and low sides of the PWM outputs end up being center aligned. 

    At the very least we need to correct this description in SysConfig so its clear how the configuration is actually happening. Your understanding of the timer registers is 100% correct though. 

    Best Regards,
    Brandon Fisher

  • 0 in reply to Brandon Fisher94
    Prodigy 155 points

    Thanks for the clarification.  I think that the difficulty I had was the mismatch between reality and expectation (based upon the reference manual examples).  It matters quite a bit to me as I'm trying to generate some fairly specific pulses with timings that change per-pulse.  I think I understand this bit of the behaviour sufficiently, now.  A description of the intended counter configuration in SysConfig would definitely have saved me a bit of head-scratching.