• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 338 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2434: ICSSG XFER2VBUS Question

AndreTseng
Intellectual 2555 points
Part Number: AM2434

Hi expert,

1.   From TRM, write command for XFER2VBUS, 17.b3 enable 64bytes mode or 32 bytes mode.

May I know how to setup R17.b3? 

Does means ldi r17.b3, 0 will set xfer2vbus in 32 bytes mode and ldi r17.b3, 1 will set xfer2vbus to 64bytes mode?

or can you please share an example code to enable 32 bytes mode?

2.  The Notes in Read Command is quite ambiguous.

Can you explain more?

If 0 -> 1, must write RD_ADDR.  What does this mean?
If 1 -> 0, must not write RD_ADDR, must drain RD_DATA/RD_CMD What does this mean?
If 0 -> 0, must write RD_ADDR What does this mean?

How to set RD_Auto mode? Can you please share an example code?

Regards

Andre

 

  • 0
    TI__Guru 54745 points

    Hi Andre,

    The experts for this matter are in holiday for next two days (11/14 - 11/15). The response may be delayed. Thanks for your patience.

    Best regards,

    Ming

  • 0 in reply to Ming Wei
    TI__Expert 6825 points

    Hello Andre,

    I will try to provide some additional information during the holiday. 

    AndreTseng said:
    May I know how to setup R17.b3? 

    This can be done in different ways, for additional information, refer to https://www.ti.com/lit/ug/spruij2/spruij2.pdf?ts=1699979551782&ref_url=https%253A%252F%252Fwww.google.com%252F 

    you can use ldi R17.b3, 0 or other methods as detailed in the assembly guide to set the bit. 

    However, 

    AndreTseng said:
    Does means ldi r17.b3, 0 will set xfer2vbus in 32 bytes mode and ldi r17.b3, 1 will set xfer2vbus to 64bytes mode?

    This is correct and by default, the xfer2vbus is in 64 bytes mode with R17.b3 set. 

    AndreTseng said:

    Can you explain more?

    If 0 -> 1, must write RD_ADDR.  What does this mean?
    If 1 -> 0, must not write RD_ADDR, must drain RD_DATA/RD_CMD What does this mean?
    If 0 -> 0, must write RD_ADDR What does this mean?

    The 0/1 represents the whether or not the xfer2vbus widget is in Read Auto Mode. When setting the value, then you must write the which address the read will start from. If the bit is set and you are to clear it, then you must pop all of the data before writing a new read address. 

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    TI__Intellectual 2555 points

    Erik,

       The link you provided is just instruction guide. Is this you want to provide me?

    In my test, no matter I set r17.b3=0 or r17.b3=1, XFER2BUS can do 64bytes mode transaction.

    Please check the following code and test result.

    In this code, I set r17.b3=0 before make 64bytes WR transaction. And load target address in R18, and R19 as 64 bytes mode.

    here is the PRU registers capture and Target address memory dump.

    I set breakpoint at the line right after 64bytes WR transaction.

    You can the result still use 64byte mode. I expected the it should write 32 bytes address to R11-R10 but I can't. 

    Can you please provide correct procedure to use 32byte mode?

    Regards

    Andre

  • 0 in reply to AndreTseng
    TI__Mastermind 44314 points
    Can you please try the following code:
    ;   Macro: m_xfr2vbus_write32
    ;
    ;   Issue write command via XFR2VBUS widget for 32 bytes
    ;
    ;   PeakCycles:
    ;       4 cycles
    ;
    ;   Invokes:
    ;       None
    ;
    ;   Registers:
    ;       r2..r9, r10:r11
    ;
    ;   PseudoCode:
    ;      (start code)
    ;       Issue xout to xfr2vbus widget with programmed address
    ;      (end code)
    ;
    ;   Parameters:
    ;       xid : instance (<XFR2VBUSP_WR0_XID>, <XFR2VBUSP_WR1_XID>)
    ;
    ;       addr_low : lower 32-bit of 48-bit external address
    ;
    ;       addr_high : upper 16-bit of 48-bit external address;
    ;
    ;   Returns:
    ;       None
    ;
    ;   See Also:
    m_xfr2vbus_write32 .macro xid, addr_low, addr_high
        ldi32 r10, addr_low
        ldi r11.w0, addr_high
        xout xid, &r2, 40
        .endm
  • 0 in reply to Nilabh Anand
    TI__Intellectual 2555 points

    Nilabh,

        Marco does work for 32 bytes mode. But I don't know what R17.B0 function is. Is TRM correct?

    Regards

    Andre

  • 0 in reply to AndreTseng
    TI__Mastermind 44314 points
    AndreTseng said:
    But I don't what R17.B0 function is. Is TRM correct?

    R17.B) does not seem to affect anything either for 32B or 64B.

    Let me check it internally with folks on this. Thanks for bringing this to our notice.