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AM2634-Q1: SPI4 read error SW reg. value does not correspond to bus value measure with logic analyzer

Nilton Spagnol Trento
Prodigy 51 points
Part Number: AM2634-Q1
Other Parts Discussed in Thread: AM2634

Hello,

We are experience some issues with the SPI4 of the AM2634 silicon revision 1.0A. 

We are having errors when reading the data package in the software, the register shows the wrong value although we see the right value in the bus by using a logic analyzer or scope.

Please see attached the picture of the register value and the logic analyzer.  

We have the same daisy chain in the SPI2 that is working normally. We are using SPI4 and SPI2 in a daisy chain with gate drives, top and bottom, so they have only minor differences in layout.

We have a RC circuit, R=100R and C=47pF, in the CLK, MOSI and MISO lines.

SPI2 works fine, with 3 or even 7 gate drives in the daisy chain. SPI4 does not work reliable, only when we changed the R to 0R it worked, but not when we have more than 3 gate drives in the daisy chain.

We cannot change the HW at this point and we would like to know if there are some ideas to solve this issue in the SW. In addition, we would like to understand why it is working in the SPI2 and not at the SPI4.

The clock goes to all the gate drives in the daisy chain and the SI does not look good at both SPI2 and SPI4, see picture of clock comparison below. 

 

  • 0
    TI__Mastermind 18500 points

    Hi Nilton, 

    Based on the oscilloscope shots you posted, I believe the problem might be due to SPI4 data/clock signal integrity. SPI4 looks worse than SPI2, so that might explain the difference in behavior.

    At what point on the PCB are you probing? For the best view of the RX behavior, you need to probe at the RX pins of the attached devices and the RX pin of the AM263x SPI controllers. 

    • Any non-monotonic rising/falling-edge behavior you see should be an instant signal integrity red-flag. Look at the magnitude of the oscillations during the rising/falling edges, and also look at the voltage levels those oscillations are occurring at. Any oscillation that can get close or passes a VIH.min or VIL.max thresholds is going to result in a logic level transition. For clock edges this means double-clocking events that latch and shift in extraneous data. For data, you just need to make sure the setup/hold times relative to the clock edges are respected. 
    • Additionally, the edge rates of all of the loaded lines look significantly low-passed. Can you check the attached gate-driver RX pin loading? Please reference the AM263x data manual SPI timing table for maximum loading conditions. 

    Adding an RC network may not be the best way to control the behavior of these clock and data edges. Multi-drop SPI channels require additional transmission-line termination analysis to work correctly. The fastest way to get a handle on this is to setup a model of your board channels in a transmission-line simulator that can utilize the IBIS IO behavior models provided on the AM263x design tools page: https://www.ti.com/product/AM2634#design-tools-simulation. 

    Thank you,

    -Randy