TM4C1290NCPDT: Question for Errata SYSCTL#23

Hi Koichiro-san,

Koichiro Tashiro said:

My customer wants to use 20MHz MOSC clock as SYSCLK source. SYSCLK is also 20MHz.
Clock phase for both clocks (MOSC and SYSCLK) must be aligned.
The customer wants to use MOSC as SYSCLK source with PLL bypass, but the errata SYSCTL#23 says it may causes "a bus fault on reset".

Question#1:
The customer tested above usecase and it works fine without any issues. 
What does "a bus fault" here exactly mean?
Are there any other conditions to cause a bus fault?

  If you are using the latest TivaWare version which is 2.2.0.295, the workaround has been implemented. 

Koichiro Tashiro said:

Question#2:
Suppose PLL is used as MOSC as PLL source, then the clock is multiplied by N and divided by N, SYSCLK frequency is configured as 20MHz.
This works as workaround, but in this case, clock phase of MOSC and SYSCLK is still aligned?
The customer afraid there are N different combination of phases.

Yes, if you use PLL to achieve 20Mhz then there will be phase shift between SYSCLK and OSCIN. 

Hi Charles,

Thanks for your quick reply! I understood Question#2.

Regarding Question#1, the customer wants to use below blue clock path to align MOSC and SYSCLK phases.


I thought the workaround in TivaWare 2.2.0.295 is not using MOSC as OSCCLK source when PLL is used.
According to your answer, phase is shifted if PLL is used.
So it does not meet the customer's requirement: MOSC and SYSCLK need to be phase aligned.
The customer tested above blue path, but no issue is observed so far. That is why they are asking Question#1.

Thanks and regards,
Koichiro Tashiro  

Hi Charles,

I close this item.
I got different question for the same Errata, so I will post another E2E item.

Thanks and regards,
Koichiro Tashiro