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LP-MSPM0G3507: Data corruption when using two ADC+DMA channels

Alan
Prodigy 155 points
Part Number: LP-MSPM0G3507
Other Parts Discussed in Thread: MSPM0G3507, SYSCONFIG

I have set up the two ADCs to repeatedly sample a single channel each, both triggered from the same event and both repeating at the same rate so they are operating simultaneously. As each one's measurement becomes available (MEM0 result loaded), DMA channels are triggered to copy the value from MEMRES[0] to a buffer. The transfer size of the two DMA channels are both set to 34 and the ADC pins are connected to the same signal source, so at the end of this process I expect to have two 34-word buffers containing identical samples (allowing for noise).

What I actually see is that one of the buffers has its second word repeated into its third location, and there is a shift in all of the values. So the buffers have samples that look like this:

Buffer B [ 0, 1, 2, 3, 4, 5, 6, 7, 8, ...,]
Buffer A [ 1, 3, 3, 4, 5, 6, 7, 8, 9, ... ]

If I set the DMA channel to use round-robin priority, the repeated word switches which buffer it appears in.

As far as I can tell, there is nothing else happening at the same time - no other DMA channels are active and the core is sitting on a WFI().

Should I be able to use two ADC+DMA channels simultaneously in this way, and is there any way of finding out why I get repeated/skewed data in the buffers?

  • 0
    TI__Mastermind 25620 points

    Hi Alan,

    I've tested this and I think there is an imbalance with your DMA settings and the ADC sampling time. I'm attaching the project that I tested with some screenshots of the arrays. I will probably add this as a code example for a future SDK.

    ADC Array 0

    ADC Array 1

    My sampling time was 20us and my input signal was a 3V sin wave at 10kHz. For the DMA, I copied the settings from the DMA ping pong example (found in the msp_subsystems folder C:\ti\mspm0_sdk_1_20_00_05\examples\nortos\LP_MSPM0G3507\msp_subsystems\adc_dma_ping_pong )

    adc_sim_dma_example.zip

    Regards,
    Luke

  • 0 in reply to Luke Ledbetter
    Prodigy 155 points

    Luke

    Thanks for the example.  I can see that you've used a much slower sample time than I have, and if I increase my sample time a little (from 300ns/sample to 400ns/sample) I can see that my issues appear to go away.  While SYSCONFIG would allow me to use this configuration, is there a rate limit on what I can expect to be simultaneously transferred to RAM buffers?

    I also see that you've used FIFO mode.  When I've tried to use your configuration in my example (and my timings) I see less skew and repetition, but there's still some small differences in the data between my two buffers, appearing periodically.  Again, should I expect to be able to perform simultaneous sampling and DMA transfer to buffers on two channels with 300ns/sample?

  • 0 in reply to Alan
    TI__Mastermind 25620 points

    Hi Alan,

    The symptom does allude to some timing issues, the DMA uses the ULPCLK. If you increase your ULPCLK from 32 MHz to 40MHz does this remove the double samples?

    Do you get an underflow or overflow error on the ADC interrupt? (Screenshot below is from the ADC-DMA/CPU Operation in FIFO Mode in the TRM)

    Regards,
    Luke

  • 0 in reply to Luke Ledbetter
    Prodigy 155 points

    I already had ULPCLK at 40MHz in my configuration, so the various symptoms I've seen have occurred with this clock speed.

    I've adjusted your example to use 40MHz ULPCLK and a total sample rate of 300ns (like this, for both ADC modules):

    When the BKPT() is hit, ADC1 is reporting an underflow condition.  If I let it run past the breakpoint, the overflow bits are set in both modules as well.

  • 0 in reply to Alan
    TI__Mastermind 25620 points

    Hi Alan,

    I won't be able to do any checks until Monday, so I can't check the 300ns on my end. The underflow condition might be why you're getting duplicate samples though or a 0 value. The overflow bits are due to the breakpoint as the ADC keeps sampling, I wouldn't fixate on the overflow if you see it from the breakpoint. You can always enable the overflow interrupt and check if the overflow happens independent of the breakpoint.

    Regards,
    Luke

  • 0 in reply to Luke Ledbetter
    Prodigy 155 points

    Thanks, it would be good to hear if you see the same variations in the data that I do when at higher sampling rates.  As the advertised maximum is 4Ms/s, I would expect to be able to take a sample every 250ns, so 300ns (if I've configured it correctly) seems like it should be possible.

    I see why the overflow happens after the breakpoint.  I'm surprised by finding that sampling faster has triggered the underflow bit.  I'll see if I can tweak settings to understand why that's happening.

  • +1 in reply to Alan
    TI__Mastermind 25620 points

    Hi Alan,

    I got to testing this and I was getting an overflow error for the ADC1 when I decreased the sampling time down to 100ns to match yours (total conversion time 300ns).The overflow error occurred because the ADC was faster than the DMA so to alleviate this I caused the DMA to trigger a bit sooner. Changing the "Enable DMA Triggers" from MEM11 result loaded interrupt to MEM9 result loaded interrupt.

    Input signal was a sin wave @100kHz from 0.5-2.5V

    Regards,
    Luke

  • 0 in reply to Luke Ledbetter
    Prodigy 155 points

    That works much better - as you've shown, the data in the buffers is now as expected.

    As a follow-up to this, a question about the DMA operation.  We've left the configuration so that 6 DMA reads are performed from the FIFO, triggered by the ADC filling MEMRES[9], so effectively starting the process before the data is fully available.  I assume that I have to rely on consistent operation to ensure that more samples will fill the FIFO while the DMA is reading earlier samples - there is no throttling in place to ensure that the DMA will wait for data in the FIFO?  Or should I be checking the under- and over-flow bits after each transfer to my buffers?  I can imagine that small changes to the ADC sample timing or to DMA priorities (with other channels) could have an impact on how full the FIFO gets.

  • 0 in reply to Alan
    TI__Mastermind 25620 points

    Hi Alan,

    In my example, the DMA would start transfers when the 9th MEM register is loaded and would run the full 6 transfers (utilizing the full fifo). If you only took 4 total samples (2 dma transfers) then the DMA wouldn't trigger to transfer. If you sampled only 10 total samples (5 dma transfers) then the DMA would still trigger but the last 2 samples would trigger an underflow flag. 

    You're right, the DMA priorities and ADC sample timing would require adjustments in your settings. There are tradeoffs with how you decide to setup your application for efficiency on the DMA bus and ADC sampling to timing requirements and priorities with other peripherals. There was a race condition between the ADC samples and the DMA trigger, which is why we needed to trigger earlier. The example code was fixed to a continuous repeat sample on the ADC, but if your application only samples so many data-points then goes to a different process, you may be able to utilize different DMA settings.

    I do not know how important the ADC samples are to your system but if they have high priority then it may be necessary to set the ADC to the highest priority and use DMA transfers on the whole fifo. If the ADC has less priority you may be able to get away with smaller DMA transfers instead of the full 6.

    Regards,
    Luke