AM2434: 16-bit parallel GPIO read with DMA

Hello,

Our expert for this topic is out of office and will return by Nov 28th, please expect a response early that week.

Regards,

Sahana

Hi jars121,

Thanks for reaching out and waiting during the US holidays.

First, let me make sure I understand your approach.
- Point 1: You know how to shift the ADC data using the R5F clock via bit banging, and point 2 and point 3 is a potential HW solution you are looking at. It sounds like point 1 is to help explain the other points and questions, is this correct?
- Point 2: It sounds like you know how to do the ADC and GPIO mapping, is this correct?
- Point 3: You are asking if linked list transfers (ideally via DMA) triggered by SPI clock can perform the shift and conversion of ADC data - which is located in a GPIO port memory. Am I understanding you clearly?

Your confirmation will help with the following question and allow me to move onto the other questions from the post.

jars121 said:

Does the above sound reasonable and is it possible using the GPIO and DMA capabilities of the Cortex R5F?

Best,
Haley

Hi Haley,

No worries at all, thank you for your prompt response, I hope you had an enjoyable holiday period.

I'll start by stating that I'm in the planning stage of the project at the moment, so everything I've noted is theoretical at this stage, based on my experience with ADC bit-banging, shifting, etc. on previous designs. I'll provide individual responses to your points below:

Haley Alexander said:

Point 1: You know how to shift the ADC data using the R5F clock via bit banging, and point 2 and point 3 is a potential HW solution you are looking at. It sounds like point 1 is to help explain the other points and questions, is this correct?

Yes this is correct. In theory, I have no issue with toggling an R5F GPIO line to shift data out of the attached ADC. On the falling edge of the R5F GPIO line (i.e. the simulated clock line) I could read the 16-bit GPI register for the conversion result. This represents the baseline or 'worst case' scenario as it's entirely software/CPU based.

Haley Alexander said:

Point 2: It sounds like you know how to do the ADC and GPIO mapping, is this correct?

Yes this is correct. I am comfortable mapping the ADC's 16 parallel output lines to a contiguous 16-bit GPI port on the AM2434. Similarly, I would be comfortable mapping either a GPIO line (bit-banging approach) or SPI clock (hardware/DMA approach) from the AM2434 to the clock input on the ADC.

Haley Alexander said:

Point 3: You are asking if linked list transfers (ideally via DMA) triggered by SPI clock can perform the shift and conversion of ADC data - which is located in a GPIO port memory. Am I understanding you clearly?

Yes this is also correct. If I can trigger an automatic read of a 16-bit GPI port (which has been correctly mapped to the 16 parallel output lines of the ADC as stated above) on the falling edge of the SPI clock, I can offload the ADC conversion read function to hardware rather than having to do so in software (i.e. bit-banging by toggling the simulated clock line as stated above). A linked list or circular buffer makes sense to me in this scenario, but I'd be open to suggestion. As there are 8 channels to read, the ideal solution would allow for 128 consecutive SPI clock transfers (16 bits per channel x 8 channels), with DMA transfer of the fixed 16-bit GPI port into 8x 16-bit buffers.

Hi jar121,

Thanks for the reply. I have the following confirmation today:

• BCDMA performs block copy from memory through vbus which has a path to gpio, so the
• There are three channels classes to chose from which will have bandwidth and latency tradeoffs.
  • This could affect throughput and your decision
  • Details are in section 11.1.1.5.2. Channel Classes of the TRM

The below items will need more time, and I'll update you on my progress by 1 Dec.

• Any additional DMA limits such as frequency
• If SPI clock is a valid trigger or event for DMA transfers
• Reviewing linked list/ring buffer part of the approach for the transfers

Since you are looking for less dependence on software in general, ADC does have a feature for hardware start of conversion, and the ADC FIFO is serviced by the DMA. Pages 6402 - 6416 may help give an additional hardware focused approach. (And pages 6417 - 6450 provide register and bit level details.)

Can you review those pages and let me know if that changes your approach at all? Or is SPI clock an important part of your implementation?

I'll still be working on the above list in the meantime.

Best,

Haley

Hi Haley,

Thanks again for your prompt response.

Haley Alexander said:

BCDMA performs block copy from memory through vbus which has a path to gpio, so the

It looks like part of your response was cut off, would you mind please revising?

Haley Alexander said:

There are three channels classes to chose from which will have bandwidth and latency tradeoffs.

• This could affect throughput and your decision
• Details are in section 11.1.1.5.2. Channel Classes of the TRM

Thank you, I'll read through the linked section in detail.

Haley Alexander said:

Since you are looking for less dependence on software in general, ADC does have a feature for hardware start of conversion, and the ADC FIFO is serviced by the DMA. Pages 6402 - 6416 may help give an additional hardware focused approach. (And pages 6417 - 6450 provide register and bit level details.)

Can you review those pages and let me know if that changes your approach at all? Or is SPI clock an important part of your implementation?

I require simultaneous sampling across the 16 analogue input channels, so I need to use external ADCs (AD7606C-16 to be precise) in this particular instance. If that weren't a hard requirement I'd be happy to use the internal multiplexed ADC which would no doubt be much easier from a DMA perspective.

Thanks!

Hi jars121,

My apologies for the cut off response, it was suppose to say "so that part of the approach looks fine."

Regarding SPI clock, rising edges on synchronous clocks count as an event. One can map these to a local or global event using DMSS INTAGGR. If issues, DMA_CLK or other clocks could be an option.

To Recap - High Level Approach Overview:

• Set up INTAGGR to map a clock to an event for DMSS triggers
• On trigger, a transfer request is sent for BCDMA to perform block copy to a gpio address

You asked for limitations. I mentioned trade offs in the previous post, but I have a few additional thoughts:

• Since you mention two ADCs and parallel outputs, the caution on page 5973 could apply if using both global event 0 for one ADC and global event 1 for another ADC.
• Since this is early in development, additional limitations cannot be found with current details

This leaves the linked list part of the post which will take a bit more time. I'll update you on my progress by 5 Dec.

Thanks,

Haley

Thank you very much Haley, I really appreciate your assistance with this set of queries.

I think I have enough to go on for the time being, but will likely reach out in the near future with follow up questions as they arise.

Thanks again!