This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TM4C123 Possible error in SSI Spec in Datasheets

Other Parts Discussed in Thread: TM4C123GH6PM, LM3S2965

Hello all!

Whilst debugging a rather insidious SSI "feature" I stumbled upon what might be an error in the TM4C123 datasheets (I have checked a few and they all have the same data). Specifically, in the Bitrate Generation section it states that for Master mode, the SSI Baud rate must be no faster than half of SysClk and no more than 25MHz. This is "confirmed" in the Spec section where it shows a minimum cycle time of 40ns. This looks like it *could* be a left-over from earlier LM3S parts which were clocked at 50MHz.

An investigation of the TivaWare source code reveals no additional checks beyond the SysClk/2 test, so TivaWare will quite happily accept up to 40MHz. Indeed, I can confirm that the TM4C123GH6PM will happily runs its SSI at 40MHz.

Further support for this theory of an incorrect value in the datasheet comes from the TM4C129 datasheets. These have the same SysClk/2 limitation but then state a maximum SSI Baud rate of 60MHz (which is indeed half of the rated 120MHz SysClk). The spec section also shows a minimum cycle time of 16.66ns. It is true that the TM4C129 devices have a revised SSI core, so it is still possible that the TM4C123 genuinely "should" not be used faster than 25MHz (and the fact that it does work at 40MHz is more luck than design), but if it is indeed an error in the datasheet, then perhaps it can be added to the Datasheet Errata ?

Cheers,

Pat.

  • Hi Pat,

    This looks like it *could* be a left-over from earlier LM3S parts which were clocked at 50MHz.

    I don't know which LM3S device you are referring. Although LM3S devices are either EOL'ed or NRND, I find one LM3S device that operates a 80Mhz and has the same SSI module as the one on the TM4C123 device limiting to 25Mhz for the SSI frequency. 

    lm3s9D92.pdf

    An investigation of the TivaWare source code reveals no additional checks beyond the SysClk/2 test, so TivaWare will quite happily accept up to 40MHz. Indeed, I can confirm that the TM4C123GH6PM will happily runs its SSI at 40MHz.

    Since the device is spec'ed for 25Mhz, the device is only characterized/qualified/tested at this speed. Although I'm glad that you are able to operate at 40Mhz but that is only for one device at room temp on the bench. Please abide by the datasheet limit.  

    Further support for this theory of an incorrect value in the datasheet comes from the TM4C129 datasheets. These have the same SysClk/2 limitation but then state a maximum SSI Baud rate of 60MHz (which is indeed half of the rated 120MHz SysClk). The spec section also shows a minimum cycle time of 16.66ns. It is true that the TM4C129 devices have a revised SSI core, so it is still possible that the TM4C123 genuinely "should" not be used faster than 25MHz (and the fact that it does work at 40MHz is more luck than design), but if it is indeed an error in the datasheet, then perhaps it can be added to the Datasheet Errata ?

    The SPI module on TM4C129 is called QSSI which is different than the SSI on TM4C123. The SSI module can operate up to 60Mhz  per TM4C129 datasheet specification. 

  • Hiya Charles!

    I have been using these devices since the early Luminary days and my head was telling me that there had been devices in the past that were 50MHz parts. The LM39D92 is what I would call a "late" Luminary part. Devices such as the LM3S2965 were clocked at 50MHz for the core, with devices like the LM3S2111 being pedestrian at 25MHz.

    You will note that it is impossible to operate the SSI at 25MHz when the core is running at 80MHz because the SSI clock needs to be an integer division of SysClk. What's worse, is if the spec really is 25MHz, then it means the later parts are inferior to the earlier ones - you can only get 20MHz without exceeding the spec, where earlier parts could do 25MHz! [arguably you could perhaps slow SysClk down to 50MHz, but that seem counterproductive]. I find it rather unlikely that TI deliberately slowed down SysClk in order to qualify the SSI module at 25MHz [though I am not discounting that possibility].

    Agreed the QSPI module is different (I did allude to that) - it's just interesting that we started with "max SysClk/2", went to "max 25MHz" only to come back to "max SysClk/2". I suppose it is possible that the SSI module was not re-validated when clocks faster than 50MHz were introduced (though I would be somewhat surprised if TI just went with an old spec and hoped for the best).

    If I were a betting man, I'd put my money on a datasheet error. It's not like those don't happen (interesting, for example, that the TM4C1294 datasheet neglects to give register descriptions for the USB core, limiting itself to only the register map - I digress).

    For the avoidance of doubt, I am not advocating that people use the parts out of spec - just that perhaps it might be sensible for someone at TI to have a good look at that spec and see if it really is legit or if it is a datasheet error.

    Cheers,


    Pat.

  • Hi Pat,

      I've tried to search the forum archive for a similar question. I found one that was answered in an internal forum by one SME who worked on both Stellaris/Tiva in the past. Since it is an internal post, I have to take a screenshot of the answer as you will not be able to view the link. There seems to be some design limitation that restricts 40Mhz. I also hope SYSCLK/2 being the limiting factor rather than 25Mhz but I cannot guarantee it will work in all conditions.  

  • Hiya Charles!

    A good thing that I am not a betting man, LOL. Good find, and that clears things up, it is not a datasheet error - though one could make the argument that it is a TivaWare error. Perhaps that could make its way into a future TivaWare release.

    Many thanks for your efforts!

    Best regards,

    Pat.