Hello All!
Whilst debugging a particularly insidious SSI "feature" I stumbled upon a bit of a short-coming of the TM4C123 Silicon Errata in the section SSI#07. It correctly states that when the EOT bit is set in the SSICR1, the SSIRIS and SSIMIS no longer correctly show the SSI TXRIS and SSI TXMIS - they do indeed read 0 even when the TX FIFO is empty. Rather unhelpfully, the suggested "fix" is to not use the EOT feature. Unfortunately that precludes the writing of an efficient SSI driver, so below some extra info that might prove helpful.
o Whilst it is true that the SSIRIS and SSIMIS do not correctly reflect the state of the SSI TXRIS and SSI TXMIS (so you can't use those reliably in your driver), the interrupt signal does still appear to make it to the NVIC - ie it still works, you just can't determine the cause of the IRQ by looking at SSIRIS / SSIMIS.
o Whilst this Erratum affects SSIRIS and SSIMIS, it does not appear to affect the SSISR - you can tell that the TX FIFO has become empty by inspecting the TFE bit.
o You can infer the cause of the IRQ if you only set one bit in the SSIIM - if there is only one enabled source, then by definition, when you enter the IRQ handler then the source must(*) have been that source, ergo you don't even need to inspect SSIRIS / MIS.
* - there is an insidious "feature" that means this is not always true, which I will detail in a separate post.
Hope this helps,
Pat.
