AM2432: What are MIIx_RXLINK (PRx_MIIx_RXLINK) pins ?

Hi

Hideaki Matsumoto said:

In the SysConfig for AM243x, there are some MIIx_RXLINK (PRx_MIIx_RXLINK) pins, but I can't find these pins in the AM243x datasheet.

We will get back on this.

Hideaki Matsumoto said:

What are these pins ?  Are these pins used for EtherCAT ?

These pins are used for fast link detection for EtherCAT. We do not use these pins for standard ethernet.

Regards
Dhaval

Hi Dhaval,

Thank you for your reply.

Dhaval Khandla said:

We will get back on this.

Thanks. Did you get any information ?

According to the Silicon Errata, MIIx_RXLINK pin can be used for the workaround of i2329 MDIO: MDIO interface corruption (CPSW and PRU-ICSS) for the standard Ethernet as well..

Could you tell us how to connect to PHY with which pins ?

Thanks and regards,

Hideaki

Hi Pratheesh,

Thank you for your reply.

As I asked at the first post, what are MIIx_RXLINK (PRx_MIIx_RXLINK) pins ? I can't find them in the datasheet.

Also, I wanted to know how to connect the pins in the case of Standard Ethernet on PRU-ICSS for the workaround of i2329.
Should MIIx_RXLINK (If it exists.) be connected to MDIO pin on PHY ?

Thanks and regards,
Hideaki

Hi Hideaki-san,

Tables 6-389, 6-390 and 6-391 in the TRM (https://www.ti.com/lit/pdf/spruim2 ) shows the mapping of the MIIx_RXLINK signals to the device signal pin names. Please let me know if this answers your question. 

I am following up internally to add a note either in Errata or DS to show this mapping easier.

Thank you,

Anita

Hi Anita,

Thank you for answering one of my questions. I could confirm the mapping of the MIIx_RXLINK signals in the TRM. Thanks!

Could I receive an answer to another question below ?

Hideaki Matsumoto said:

Also, I wanted to know how to connect the pins in the case of Standard Ethernet on PRU-ICSS for the workaround of i2329.
Should MIIx_RXLINK (If it exists.) be connected to MDIO pin on PHY ?

Thanks and regards,
Hideaki

Hideaki Matsumoto said:

Also, I wanted to know how to connect the pins in the case of Standard Ethernet on PRU-ICSS for the workaround of i2329.
Should MIIx_RXLINK (If it exists.) be connected to MDIO pin on PHY ?

No, to LED_SPEED or LED_LINK output of PHY which is a stable link indication (active high, active low polarity is ok)

Hi Pratheesh,

Thank you for your answer. Please allow me ask you one more thing. There are the Workaround descriptions for i2329 in Errata below. Which case is the part written in red the description for EtherCAT or Standard Ethernet ?

----------------------------

Workaround(s): On affected devices, following workaround should be used:

MDIO manual mode: applicable for PRU-ICSS and for CPSW.

MDIO protocol can be emulated by reading and writing to the appropriate bits within the MDIO_MANUAL_IF_REG register of the MDIO peripheral to directly manipulate the MDIO clock and data pins. Refer to TRM for full details of manual mode register bits and their function.

In this case the device pin multiplexing should be configured to allow the IO to be controlled by the CPSW or PRU-ICSS peripherals (same as in normal intended operation), but the MDIO state machine must be disabled by ensuring MDIO_CONTROL_REG.ENABLE bit is 0 in the MDIO_CONTROL_REG and enable manual mode by setting MDIO_POLL_REG.MANUALMODE bit to 1.

In case of PRU-ICSS, the loading of the software workaround may be reduced by using the MLINK feature of MDIO to do automatic polling of link status via the MIIx_RXLINK input pin to PRU-ICSS which must be connected to a status output from the external PHY which does not toggle while the link is active. Depending on the specified behavior of the external PHY device, this PHY status output may be LED_LINK or LED_SPEED or the logic OR of LED_LINK and LED SPEED. Refer to the MDIO section of TRM for details on using the MLINK feature of MDIO. This feature is not available on the CPSW peripheral.

For EtherCAT implementation on PRU-ICSS, the software workaround will be done in RTUx/ TX_PRUx Core. The core will have to be dedicated for workaround, which means this can’t be used for other purpose. The implementation will support two user access channels for MDIO access. This provides option for R5f core and PRU core to have independent access channel. The APIs will be similar to the ones we will have in RTOS Workaround implementation. EtherCAT will continue to use PHY fast link detection via MDIO MLINK bypassing state m/c for link status (as this path is not affected by errata). This makes sure that cable redundancy related latency requirements are still met.

----------------------------

Thanks and regards,

Hideaki

Hi Pratheesh,

Thank you for your reply. Let me doublecheck. The above workaround description written in red is NOT applied to the Standard Ethernet. Correct ? 

Thanks and regards,
Hideaki

Hello,

I'm working with Matsumoto-san for this topic.
Let me confirm one thing. For standard ethernet usecase, is it OK to assign this PRx_MIIx_RXLINK pins to other functions?

Regards,
Oba

Oba said:

For standard ethernet usecase, is it OK to assign this PRx_MIIx_RXLINK pins to other functions?

Yes

Thanks for your very quick support!

Regards,
oba